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baytrail: initialize common SSC functionality 

The SSC (storage control cluster) houses the SD, SDIO, and eMMC
interfaces. The scc cofniguration function, baytrail_init_scc(),
is ran in the pre device stage to initialize the SCC. The eMMC
is expected to be configured for version 4.5.

BUG=chrome-os-partner:23966
BRANCH=None
TEST=Built and booted with some other eMMC changes into login screen off
     of eMMC device.

Change-Id: I81cc755a790b7e43ad234a8201dae480277202c8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176535
Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4966
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Aaron Durbin 2013-11-12 16:40:33 -06:00 committed by Kyösti Mälkki
parent e8f97d4f55
commit c626b74c1d
4 changed files with 87 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/soc/intel/baytrail/Makefile.inc
View File

@ -39,6 +39,7 @@ ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c
ramstage-y += sata.c ramstage-y += sata.c
ramstage-y += acpi.c ramstage-y += acpi.c
ramstage-y += lpe.c ramstage-y += lpe.c
ramstage-y += scc.c
# Remove as ramstage gets fleshed out # Remove as ramstage gets fleshed out
ramstage-y += placeholders.c ramstage-y += placeholders.c

1
src/soc/intel/baytrail/baytrail/ramstage.h
View File

@ -33,6 +33,7 @@ void baytrail_run_reference_code(void);
#else #else
static inline void baytrail_run_reference_code(void) {} static inline void baytrail_run_reference_code(void) {}
#endif #endif
void baytrail_init_scc(void);
extern struct pci_operations soc_pci_ops; extern struct pci_operations soc_pci_ops;

2
src/soc/intel/baytrail/ramstage.c
View File

@ -166,6 +166,8 @@ void baytrail_init_pre_device(void)
config = mainboard_get_gpios(); config = mainboard_get_gpios();
setup_soc_gpios(config); setup_soc_gpios(config);
baytrail_init_scc();
/* Indicate S3 resume to rest of ramstage. */ /* Indicate S3 resume to rest of ramstage. */
s3_resume_prepare(); s3_resume_prepare();
} }

83
src/soc/intel/baytrail/scc.c Normal file
View File

@ -0,0 +1,83 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <console/console.h>
#include <reg_script.h>
#include <baytrail/iosf.h>
#include <baytrail/ramstage.h>
static const struct reg_script scc_start_dll[] = {
/* Configure master DLL. */
REG_IOSF_WRITE(IOSF_PORT_SCORE, 0x4964, 0x00078000),
/* Configure Swing,FSM for Master DLL */
REG_IOSF_WRITE(IOSF_PORT_SCORE, 0x4970, 0x00000133),
/* Run+Local Reset on Master DLL */
REG_IOSF_WRITE(IOSF_PORT_SCORE, 0x4970, 0x00001933),
REG_SCRIPT_END,
};
static const struct reg_script scc_after_dll[] = {
/* Configure Write Path */
REG_IOSF_RMW(IOSF_PORT_SCORE, 0x4954, ~0x7fff, 0x35ad),
REG_IOSF_RMW(IOSF_PORT_SCORE, 0x4958, ~0x7fff, 0x35ad),
REG_IOSF_RMW(IOSF_PORT_SCORE, 0x495c, ~0x7fff, 0x35ad),
/* Configure Read Path */
REG_IOSF_RMW(IOSF_PORT_SCORE, 0x43e4, ~0x7fff, 0x35ad),
REG_IOSF_RMW(IOSF_PORT_SCORE, 0x4324, ~0x7fff, 0x35ad),
REG_IOSF_RMW(IOSF_PORT_SCORE, 0x42b4, ~0x7fff, 0x35ad),
/* eMMC 4.5 TX and RX DLL */
REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49a4, ~0x1f001f, 0xa000d),
REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49a8, ~0x1f001f, 0xd000d),
REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49ac, ~0x1f001f, 0xd000d),
REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49b0, ~0x1f001f, 0xd000d),
REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49b4, ~0x1f001f, 0xd000d),
REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49b8, ~0x1, 0x0),
/* cfio_regs_mmc1_ELECTRICAL.nslew/pslew */
REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c0, ~0x3c, 0x0),
REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c4, ~0x3c, 0x0),
/*
* iosf2ocp_private.GENREGRW1.cr_clock_enable_clk_ocp = 01
* iosf2ocp_private.GENREGRW1.cr_clock_enable_clk_xin = 01
*/
REG_IOSF_RMW(IOSF_PORT_SCC, 0x600, ~0xf, 0x5),
/* Enable IOSF Snoop */
REG_IOSF_OR(IOSF_PORT_SCC, 0x00, (1 << 7)),
/* SDIO 3V Support. */
REG_IOSF_RMW(IOSF_PORT_SCC, 0x600, ~0x30, 0x30),
REG_SCRIPT_END,
};
void baytrail_init_scc(void)
{
uint32_t dll_values;
printk(BIOS_DEBUG, "Initializing sideband SCC registers.\n");
/* Common Sideband Initialization for SCC */
reg_script_run(scc_start_dll);
/* Override Slave Path - populate DLL settings. */
dll_values = iosf_score_read(0x496c) & 0x7ffff;
dll_values |= iosf_score_read(0x4950) & ~0xfffff;
iosf_score_write(0x4950, dll_values | (1 << 19));
reg_script_run(scc_after_dll);
}