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soc/intel/tigerlake: Update DCACHE_BSP_STACK_SIZE 

According to the latest Tigerlake Platform FSP Integration Guide, the
minimum amount of stack needed for FSP-M is 256KiB. Change
DCACHE_BSP_STACK_SIZE to reflect that (plus 1KB previously determined
empirically). JSL requires 192KiB.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ic9be6446c4db7f62479deab06ebeba2c7326e681
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This commit is contained in:
Tim Wawrzynczak 2020-03-20 10:58:51 -06:00 committed by Patrick Georgi
parent 4629830b73
commit c632bda2f6
1 changed files with 4 additions and 2 deletions
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6
src/soc/intel/tigerlake/Kconfig
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@ -84,11 +84,13 @@ config DCACHE_RAM_SIZE
config DCACHE_BSP_STACK_SIZE
hex
default 0x30400
default 0x40400 if SOC_INTEL_TIGERLAKE
default 0x30400 if SOC_INTEL_JASPERLAKE
help
The amount of anticipated stack usage in CAR by bootblock and
other stages. In the case of FSP_USES_CB_STACK default value will be
sum of FSP-M stack requirement (192KiB) and CB romstage stack requirement (~1KiB).
sum of FSP-M stack requirement (256KiB for TGL, 192KiB for JSL) and CB romstage
stack requirement (~1KiB).
config FSP_TEMP_RAM_SIZE
hex