diff --git a/src/mainboard/intel/shadowmountain/Kconfig b/src/mainboard/intel/shadowmountain/Kconfig
index a8f7bf5d9e..e42160fd1a 100644
--- a/src/mainboard/intel/shadowmountain/Kconfig
+++ b/src/mainboard/intel/shadowmountain/Kconfig
@@ -20,6 +20,8 @@ config BOARD_SPECIFIC_OPTIONS
 	select HAVE_SPD_IN_CBFS
 	select INTEL_LPSS_UART_FOR_CONSOLE
 	select MAINBOARD_HAS_CHROMEOS
+	select MAINBOARD_HAS_SPI_TPM_CR50
+	select MAINBOARD_HAS_TPM2
 	select PCIEXP_HOTPLUG
 	select SOC_INTEL_ALDERLAKE
 	select SOC_INTEL_CSE_LITE_SKU
@@ -34,7 +36,6 @@ config CHROMEOS
 config VBOOT
 	select EC_GOOGLE_CHROMEEC_SWITCHES
 	select VBOOT_LID_SWITCH
-	select VBOOT_MOCK_SECDATA
 	select HAS_RECOVERY_MRC_CACHE
 
 config DIMM_SPD_SIZE
@@ -69,4 +70,11 @@ config PCIEXP_HOTPLUG_PREFETCH_MEM
 	hex
 	default 0x1c000000 # 448 MiB
 
+config DRIVER_TPM_SPI_BUS
+	default 0x1
+
+config TPM_TIS_ACPI_INTERRUPT
+	int
+	default 3	# GPE0_DW0_3 (GPP_C3)
+
 endif # BOARD_INTEL_SHADOWMOUNTAIN
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
index 98f64008a5..8b3178408d 100644
--- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
@@ -311,7 +311,14 @@ chip soc/intel/alderlake
 		device pci 1d.3 off end # RP12
 		device pci 1e.0 on  end # UART0
 		device pci 1e.1 off end # UART1
-		device pci 1e.2 on  end # GSPI0
+		device pci 1e.2 on
+			chip drivers/spi/acpi
+				register "hid" = "ACPI_DT_NAMESPACE_HID"
+				register "compat_string" = ""google,cr50""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C3_IRQ)"
+				device spi 0 on end
+			end
+		end # GSPI0
 		device pci 1e.3 off end # GSPI1
 		device pci 1f.0 on
 			chip ec/google/chromeec