google/panther: acpi: Fix unstable fan behavior on boot + resume
FLVL is used to keep track of which thermal zones are active, but it is not initialized upon boot / resume. An initial value of zero corresponds to all zones being active, which causes the fan to spin at max speed until the OS changes zones. Fix this annoyance by initializing FLVL to the lowest temperature zone. Also, fix a related bug where FLVL may jump to an undesired value. For example, if FLVL=3 (zones 3 + 4 active), and zone 0 is set to off (it's already off!), FLVL would previously become 1 (zones 1 + 2 + 3 + 4 active!). Fix this by not taking zone ON / OFF actions if our zone is already ON / OFF. BUG=chrome-os-partner:25766, chrome-os-partner:24775 TEST=Suspend / resume on Panther 20 times, verify that thermal zone after resume matches expectation based upon temperature. Also, stress system and verify thermal zones become active according to temperature increase. Change-Id: Ic60686aa5a67bf40c17497832b086ba09d56111a Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/186455 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/186669 Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/6006 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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@ -68,5 +68,8 @@ Method(_PTS,1)
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Method(_WAK,1)
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{
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/* Initialize thermal defaults */
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\_TZ.THRM._INI ()
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Return(Package(){0,0})
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}
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@ -61,6 +61,14 @@ Scope (\_TZ)
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Return (\PPKG ())
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}
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// Start fan at state 4 = lowest temp state
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Method (_INI)
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{
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Store (4, \FLVL)
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Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
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Notify (\_TZ.THRM, 0x81)
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}
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Method (TCHK, 0, Serialized)
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{
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// Get CPU Temperature from PECI via SuperIO TMPIN3
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@ -170,14 +178,20 @@ Scope (\_TZ)
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}
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}
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Method (_ON) {
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Store (0, \FLVL)
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Store (\F0PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
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Notify (\_TZ.THRM, 0x81)
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If (LNot (_STA ())) {
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Store (0, \FLVL)
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Store (\F0PW,
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\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
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Notify (\_TZ.THRM, 0x81)
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}
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}
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Method (_OFF) {
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Store (1, \FLVL)
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Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
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Notify (\_TZ.THRM, 0x81)
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If (_STA ()) {
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Store (1, \FLVL)
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Store (\F1PW,
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\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
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Notify (\_TZ.THRM, 0x81)
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}
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}
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}
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@ -191,14 +205,20 @@ Scope (\_TZ)
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}
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}
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Method (_ON) {
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Store (1, \FLVL)
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Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
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Notify (\_TZ.THRM, 0x81)
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If (LNot (_STA ())) {
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Store (1, \FLVL)
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Store (\F1PW,
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\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
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Notify (\_TZ.THRM, 0x81)
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}
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}
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Method (_OFF) {
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Store (2, \FLVL)
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Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
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Notify (\_TZ.THRM, 0x81)
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If (_STA ()) {
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Store (2, \FLVL)
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Store (\F2PW,
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\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
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Notify (\_TZ.THRM, 0x81)
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}
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}
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}
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@ -212,14 +232,20 @@ Scope (\_TZ)
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}
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}
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Method (_ON) {
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Store (2, \FLVL)
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Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
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Notify (\_TZ.THRM, 0x81)
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If (LNot (_STA ())) {
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Store (2, \FLVL)
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Store (\F2PW,
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\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
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Notify (\_TZ.THRM, 0x81)
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}
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}
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Method (_OFF) {
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Store (3, \FLVL)
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Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
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Notify (\_TZ.THRM, 0x81)
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If (_STA ()) {
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Store (3, \FLVL)
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Store (\F3PW,
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\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
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Notify (\_TZ.THRM, 0x81)
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}
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}
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}
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@ -233,14 +259,20 @@ Scope (\_TZ)
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}
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}
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Method (_ON) {
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Store (3, \FLVL)
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Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
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Notify (\_TZ.THRM, 0x81)
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If (LNot (_STA ())) {
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Store (3, \FLVL)
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Store (\F3PW,
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\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
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Notify (\_TZ.THRM, 0x81)
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}
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}
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Method (_OFF) {
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Store (4, \FLVL)
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Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
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Notify (\_TZ.THRM, 0x81)
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If (_STA ()) {
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Store (4, \FLVL)
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Store (\F4PW,
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\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
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Notify (\_TZ.THRM, 0x81)
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}
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}
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}
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@ -254,14 +286,20 @@ Scope (\_TZ)
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}
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}
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Method (_ON) {
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Store (4, \FLVL)
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Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
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Notify (\_TZ.THRM, 0x81)
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If (LNot (_STA ())) {
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Store (4, \FLVL)
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Store (\F4PW,
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\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
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Notify (\_TZ.THRM, 0x81)
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}
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}
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Method (_OFF) {
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Store (4, \FLVL)
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Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
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Notify (\_TZ.THRM, 0x81)
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If (_STA ()) {
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Store (4, \FLVL)
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Store (\F4PW,
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\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
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Notify (\_TZ.THRM, 0x81)
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}
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}
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}
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