cpu/intel/car: Prepare for C_ENVIRONMENT_BOOTBLOCK
Pass timestamps and BIST to romstage using the same signature as C_ENVIRONMENT_BOOTBLOCK will. Change-Id: Ic90da6b1b5ac3b56c69b593ba447ed8e05c8a4e2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki
parent
ee2e936f40
commit
c641f7ed9f
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@ -22,11 +22,12 @@
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#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
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#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
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.global bootblock_pre_c_entry
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.code32
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_cache_as_ram_setup:
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/* Save the BIST result. */
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movl %eax, %ebp
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bootblock_pre_c_entry:
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cache_as_ram:
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post_code(0x20)
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@ -167,22 +168,24 @@ addrsize_set_high:
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movl %eax, %cr0
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/* Setup the stack. */
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movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax
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movl %eax, %esp
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/* Align the stack 16 bytes */
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mov $_car_stack_end, %esp
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/* Need to align stack to 16 bytes at call instruction. Account for
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the pushes below. */
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andl $0xfffffff0, %esp
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/* Account for pushing the BIST result */
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subl $12, %esp
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subl $4, %esp
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/* Restore the BIST result. */
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movl %ebp, %eax
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movl %esp, %ebp
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pushl %eax
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/* push TSC and BIST to stack */
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movd %mm0, %eax
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pushl %eax /* BIST */
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movd %mm2, %eax
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pushl %eax /* tsc[63:32] */
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movd %mm1, %eax
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pushl %eax /* tsc[31:0] */
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before_romstage:
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before_c_entry:
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post_code(0x29)
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/* Call romstage.c main function. */
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call romstage_main
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call bootblock_c_entry_bist
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/* Should never see this postcode */
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post_code(POST_DEAD_CODE)
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@ -25,11 +25,12 @@
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#define NoEvictMod_MSR 0x2e0
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.global bootblock_pre_c_entry
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.code32
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_cache_as_ram_setup:
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/* Save the BIST result. */
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movl %eax, %ebp
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bootblock_pre_c_entry:
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cache_as_ram:
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post_code(0x20)
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@ -171,23 +172,24 @@ addrsize_set_high:
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movl %eax, %cr0
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/* Setup the stack. */
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movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax
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movl %eax, %esp
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mov $_car_stack_end, %esp
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/* Align the stack 16 bytes */
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/* Need to align stack to 16 bytes at call instruction. Account for
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the pushes below. */
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andl $0xfffffff0, %esp
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/* Account for pushing the BIST result */
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subl $12, %esp
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subl $4, %esp
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/* Restore the BIST result. */
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movl %ebp, %eax
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movl %esp, %ebp
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pushl %eax
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/* push TSC and BIST to stack */
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movd %mm0, %eax
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pushl %eax /* BIST */
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movd %mm2, %eax
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pushl %eax /* tsc[63:32] */
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movd %mm1, %eax
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pushl %eax /* tsc[31:0] */
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before_romstage:
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before_c_entry:
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post_code(0x29)
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/* Call romstage.c main function. */
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call romstage_main
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call bootblock_c_entry_bist
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/* Should never see this postcode */
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post_code(POST_DEAD_CODE)
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@ -23,11 +23,12 @@
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#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
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#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
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.global bootblock_pre_c_entry
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.code32
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_cache_as_ram_setup:
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/* Save the BIST result. */
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movl %eax, %ebp
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bootblock_pre_c_entry:
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cache_as_ram:
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post_code(0x20)
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@ -156,18 +157,24 @@ addrsize_set_high:
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movl %eax, %cr0
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/* Setup the stack. */
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movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax
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movl %eax, %esp
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mov $_car_stack_end, %esp
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/* Restore the BIST result. */
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movl %ebp, %eax
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movl %esp, %ebp
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pushl %eax
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/* Need to align stack to 16 bytes at call instruction. Account for
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the pushes below. */
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andl $0xfffffff0, %esp
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subl $4, %esp
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before_romstage:
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post_code(0x2f)
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/* Call romstage.c main function. */
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call romstage_main
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/* push TSC and BIST to stack */
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movd %mm0, %eax
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pushl %eax /* BIST */
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movd %mm2, %eax
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pushl %eax /* tsc[63:32] */
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movd %mm1, %eax
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pushl %eax /* tsc[31:0] */
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before_c_entry:
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post_code(0x29)
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call bootblock_c_entry_bist
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/* Should never see this postcode */
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post_code(POST_DEAD_CODE)
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@ -28,11 +28,12 @@
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#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
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#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
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.global bootblock_pre_c_entry
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.code32
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_cache_as_ram_setup:
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/* Save the BIST result. */
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movl %eax, %ebp
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bootblock_pre_c_entry:
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cache_as_ram:
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post_code(0x20)
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@ -353,22 +354,24 @@ skip_cache_rom:
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movl %eax, %cr0
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/* Setup the stack. */
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movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax
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movl %eax, %esp
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/* Align the stack 16 bytes */
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mov $_car_stack_end, %esp
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/* Need to align stack to 16 bytes at call instruction. Account for
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the pushes below. */
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andl $0xfffffff0, %esp
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/* Account for pushing the BIST result */
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subl $12, %esp
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subl $4, %esp
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/* Restore the BIST result. */
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movl %ebp, %eax
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movl %esp, %ebp
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pushl %eax
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/* push TSC and BIST to stack */
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movd %mm0, %eax
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pushl %eax /* BIST */
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movd %mm2, %eax
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pushl %eax /* tsc[63:32] */
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movd %mm1, %eax
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pushl %eax /* tsc[31:0] */
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before_romstage:
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before_c_entry:
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post_code(0x2f)
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/* Call romstage.c main function. */
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call romstage_main
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call bootblock_c_entry_bist
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/* Should never see this postcode */
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post_code(POST_DEAD_CODE)
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@ -11,6 +11,7 @@
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* GNU General Public License for more details.
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*/
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#include <bootblock_common.h>
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#include <console/console.h>
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#include <cpu/intel/romstage.h>
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#include <cpu/x86/mtrr.h>
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@ -19,7 +20,7 @@
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#define DCACHE_RAM_ROMSTAGE_STACK_SIZE 0x2000
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asmlinkage void *romstage_main(unsigned long bist)
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static void romstage_main(unsigned long bist)
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{
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int i;
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const int num_guards = 4;
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@ -50,7 +51,12 @@ asmlinkage void *romstage_main(unsigned long bist)
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}
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platform_enter_postcar();
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/* We do not return. */
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return NULL;
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}
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/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK,
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* keeping changes in cache_as_ram.S easy to manage.
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*/
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asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist)
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{
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romstage_main(bist);
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}
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@ -7,8 +7,4 @@ void mainboard_romstage_entry(unsigned long bist);
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void platform_enter_postcar(void);
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/* romstage_main is called from the cache-as-ram assembly file to prepare
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* CAR stack guards.*/
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asmlinkage void *romstage_main(unsigned long bist);
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#endif /* _CPU_INTEL_ROMSTAGE_H */
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@ -31,8 +31,7 @@ struct romstage_params {
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void mainboard_romstage_entry(struct romstage_params *params);
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void romstage_common(struct romstage_params *params);
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void *asmlinkage romstage_main(unsigned long bist, uint32_t tsc_lo,
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uint32_t tsc_high);
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void raminit(struct mrc_params *mp, int prev_sleep_state);
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void gfx_init(void);
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void tco_disable(void);
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@ -176,23 +176,24 @@ addrsize_set_high:
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post_code(0x29)
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/* Setup the stack. */
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movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax
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movl %eax, %esp
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mov $_car_stack_end, %esp
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/* Push the initial TSC value from boot block. The low 32 bits are
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* in mm1, and the high 32 bits are in mm2. */
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movd %mm2, %eax
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pushl %eax
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movd %mm1, %eax
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pushl %eax
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/* Restore the BIST result. */
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/* Need to align stack to 16 bytes at call instruction. Account for
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the pushes below. */
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andl $0xfffffff0, %esp
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subl $4, %esp
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/* push TSC and BIST to stack */
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movd %mm0, %eax
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pushl %eax
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pushl %eax /* BIST */
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movd %mm2, %eax
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pushl %eax /* tsc[63:32] */
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movd %mm1, %eax
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pushl %eax /* tsc[31:0] */
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before_romstage:
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before_c_entry:
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post_code(0x2a)
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/* Call romstage.c main function. */
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call romstage_main
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call bootblock_c_entry_bist
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/* Should never see this postcode */
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post_code(POST_DEAD_CODE)
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@ -17,6 +17,7 @@
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#include <arch/cpu.h>
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#include <arch/io.h>
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#include <arch/early_variables.h>
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#include <bootblock_common.h>
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#include <console/console.h>
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#include <cbmem.h>
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#include <cpu/x86/mtrr.h>
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@ -95,8 +96,7 @@ static void spi_init(void)
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}
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/* Entry from cache-as-ram.inc. */
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void *asmlinkage romstage_main(unsigned long bist, uint32_t tsc_low,
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uint32_t tsc_hi)
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static void romstage_main(uint64_t tsc, uint32_t bist)
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{
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struct romstage_params rp = {
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.bist = bist,
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@ -104,7 +104,7 @@ void *asmlinkage romstage_main(unsigned long bist, uint32_t tsc_low,
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};
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/* Save initial timestamp from bootblock. */
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timestamp_init((((uint64_t)tsc_hi) << 32) | (uint64_t)tsc_low);
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timestamp_init(tsc);
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/* Save romstage begin */
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timestamp_add_now(TS_START_ROMSTAGE);
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@ -131,7 +131,14 @@ void *asmlinkage romstage_main(unsigned long bist, uint32_t tsc_low,
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platform_enter_postcar();
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/* We don't return here */
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return NULL;
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}
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/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK,
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* keeping changes in cache_as_ram.S easy to manage.
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*/
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asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist)
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{
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romstage_main(base_timestamp, bist);
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}
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static struct chipset_power_state power_state CAR_GLOBAL;
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@ -29,8 +29,7 @@ struct romstage_params {
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void mainboard_romstage_entry(struct romstage_params *params);
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void romstage_common(struct romstage_params *params);
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asmlinkage void *romstage_main(unsigned long bist, uint32_t tsc_lo,
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uint32_t tsc_high);
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void raminit(struct pei_data *pei_data);
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struct chipset_power_state;
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@ -18,6 +18,7 @@
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#include <arch/io.h>
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#include <arch/cbfs.h>
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#include <arch/early_variables.h>
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#include <bootblock_common.h>
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#include <bootmode.h>
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#include <cbmem.h>
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#include <console/console.h>
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@ -64,8 +65,7 @@ static void platform_enter_postcar(void)
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}
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/* Entry from cache-as-ram.inc. */
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asmlinkage void *romstage_main(unsigned long bist,
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uint32_t tsc_low, uint32_t tsc_hi)
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static void romstage_main(uint64_t tsc, uint32_t bist)
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{
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struct romstage_params rp = {
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.bist = bist,
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post_code(0x30);
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/* Save initial timestamp from bootblock. */
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timestamp_init((((uint64_t)tsc_hi) << 32) | (uint64_t)tsc_low);
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timestamp_init(tsc);
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/* Save romstage begin */
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timestamp_add_now(TS_START_ROMSTAGE);
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mainboard_romstage_entry(&rp);
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platform_enter_postcar();
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}
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return NULL;
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/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK,
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* keeping changes in cache_as_ram.S easy to manage.
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*/
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asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist)
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{
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romstage_main(base_timestamp, bist);
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}
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/* Entry from the mainboard. */
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