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nb/intel/ironlake: Add Generic Non-Core PCI device definition

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Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.

Change-Id: I8feff0d71ad70ac994e29b238d35e2c73aa92ecd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Angel Pons 2020-07-22 18:21:43 +02:00 committed by Patrick Georgi
parent a457e35237
commit c642a0d894
3 changed files with 9 additions and 4 deletions
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2
src/northbridge/intel/ironlake/early_init.c
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@ -43,7 +43,7 @@ static void early_cpu_init(void)
/* bit 0 = disable multicore, /* bit 0 = disable multicore,
bit 1 = disable quadcore, bit 1 = disable quadcore,
bit 8 = disable hyperthreading. */ bit 8 = disable hyperthreading. */
pci_update_config32(PCI_DEV(0xff, 0x00, 0), 0x80, 0xfffffefc, 0x10000); pci_update_config32(QPI_NON_CORE, 0x80, 0xfffffefc, 0x10000);
u8 reg8; u8 reg8;
struct cpuid_result result; struct cpuid_result result;

5
src/northbridge/intel/ironlake/ironlake.h
View file

@ -47,6 +47,11 @@
#include "hostbridge_regs.h" #include "hostbridge_regs.h"
/*
* Generic Non-Core Registers
*/
#define QPI_NON_CORE PCI_DEV(QUICKPATH_BUS, 0, 0)
/* /*
* SAD - System Address Decoder * SAD - System Address Decoder
*/ */

6
src/northbridge/intel/ironlake/raminit.c
View file

@ -3955,8 +3955,8 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
pci_read_config32(QPI_LINK_0, QPI_DEF_RMT_VN_CREDITS); // !!!! pci_read_config32(QPI_LINK_0, QPI_DEF_RMT_VN_CREDITS); // !!!!
pci_write_config32(QPI_LINK_0, QPI_DEF_RMT_VN_CREDITS, 0x64555); pci_write_config32(QPI_LINK_0, QPI_DEF_RMT_VN_CREDITS, 0x64555);
pci_read_config32(QPI_LINK_0, QPI_DEF_RMT_VN_CREDITS); // !!!! pci_read_config32(QPI_LINK_0, QPI_DEF_RMT_VN_CREDITS); // !!!!
pci_read_config32(PCI_DEV (0xff, 0, 0), 0xd0); // !!!! pci_read_config32(QPI_NON_CORE, 0xd0); // !!!!
pci_write_config32(PCI_DEV (0xff, 0, 0), 0xd0, 0x180); pci_write_config32(QPI_NON_CORE, 0xd0, 0x180);
gav(MCHBAR32(0x1af0)); // !!!! gav(MCHBAR32(0x1af0)); // !!!!
gav(MCHBAR32(0x1af0)); // !!!! gav(MCHBAR32(0x1af0)); // !!!!
MCHBAR32(0x1af0) = 0x1f020003; MCHBAR32(0x1af0) = 0x1f020003;
@ -4225,7 +4225,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
MCHBAR8(0x2ca8) = MCHBAR8(0x2ca8); MCHBAR8(0x2ca8) = MCHBAR8(0x2ca8);
MCHBAR32_AND_OR(0x2c80, 0, 0x53688); // !!!! MCHBAR32_AND_OR(0x2c80, 0, 0x53688); // !!!!
pci_write_config32(PCI_DEV (0xff, 0, 0), 0x60, 0x20220); pci_write_config32(QPI_NON_CORE, 0x60, 0x20220);
MCHBAR16(0x2c20); // !!!! MCHBAR16(0x2c20); // !!!!
MCHBAR16(0x2c10); // !!!! MCHBAR16(0x2c10); // !!!!
MCHBAR16(0x2c00); // !!!! MCHBAR16(0x2c00); // !!!!