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soc/amd/picasso/aoac: Set the Target Device State when powering on 

If the OS sets the target device state to D3, we need to clear it so we
can reestablish register access.

BUG=b:153001807
TEST=Boot trembyle with I2C powered off and see it power back on.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: If9bd1b7cfa7b8d074226c4dcdefc1a44cad8b940
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Raul E Rangel 2020-06-11 14:08:17 -06:00 committed by Patrick Georgi
parent d53c281d0b
commit c64755bcd7
2 changed files with 6 additions and 0 deletions
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2
src/soc/amd/picasso/aoac.c
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@ -36,6 +36,8 @@ void power_on_aoac_device(int dev)
/* Power on the UART and AMBA devices */
byte = aoac_read8(AOAC_DEV_D3_CTL(dev));
byte |= FCH_AOAC_PWR_ON_DEV;
byte &= ~FCH_AOAC_TARGET_DEVICE_STATE;
byte |= FCH_AOAC_D0_INITIALIZED;
aoac_write8(AOAC_DEV_D3_CTL(dev), byte);
}

4
src/soc/amd/picasso/include/soc/southbridge.h
View File

@ -207,6 +207,10 @@
/* Bit definitions for Device D3 Control AOACx0000[40...7E] step 2 */
#define FCH_AOAC_TARGET_DEVICE_STATE (BIT(0) + BIT(1))
#define FCH_AOAC_D0_UNINITIALIZED 0
#define FCH_AOAC_D0_INITIALIZED 1
#define FCH_AOAC_D1_2_3_WARM 2
#define FCH_AOAC_D3_COLD 3
#define FCH_AOAC_DEVICE_STATE BIT(2)
#define FCH_AOAC_PWR_ON_DEV BIT(3)
#define FCH_AOAC_SW_PWR_ON_RSTB BIT(4)