soc/intel/apollolake: provide power button ACPI device

Instead of having each mainboard provide the power button,
uncondtionally provide the power button ACPI device on behalf
of each mainboard.

BUG=chrome-os-partner:56677

Change-Id: I94c9e0353c8d829136f0d52a356286c6bedcddd5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16731
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

src/mainboard/google/reef/dsdt.asl

@@ -46,7 +46,7 @@ DefinitionBlock(
 	/* Chipset specific sleep states */
 	#include <soc/intel/apollolake/acpi/sleepstates.asl>
 
-	/* LID and Power button. */
+	/* LID  */
 	Scope (\_SB)
 	{
 		Device (LID0)
@@ -58,11 +58,6 @@ DefinitionBlock(
 			}
 			Name (_PRW, Package () { GPE_EC_WAKE, 0x3 })
 		}
-
-		Device (PWRB)
-		{
-			Name (_HID, EisaId ("PNP0C0C"))
-		}
 	}
 
 	/* Chrome OS Embedded Controller */

src/soc/intel/apollolake/acpi/southbridge.asl

@@ -17,6 +17,15 @@
 
 #include <soc/gpe.h>
 
+/* Power button. */
+Scope (\_SB)
+{
+	Device (PWRB)
+	{
+		Name (_HID, EisaId ("PNP0C0C"))
+	}
+}
+
 /* PCIE device */
 #include "pcie.asl"