soc/intel/cannonlake: Add cpu.asl file
This patch adds the cpu.asl file in cnl. We are only defining the PNOT method here in this patch as this is needed by the ec/google/chromeec/acpi/ec.asl file for the AC methods. TEST= code compiles and boots when we include the ec.asl file. Change-Id: Id93012833fac116d4d7514aa2d0b8493d2f666a9 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/22365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* These devices are created at runtime */
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External (\_PR.CP00, DeviceObj)
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External (\_PR.CP01, DeviceObj)
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External (\_PR.CP02, DeviceObj)
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External (\_PR.CP03, DeviceObj)
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External (\_PR.CP04, DeviceObj)
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External (\_PR.CP05, DeviceObj)
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External (\_PR.CP06, DeviceObj)
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External (\_PR.CP07, DeviceObj)
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/* Notify OS to re-read CPU tables, assuming ^2 CPU count */
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Method (PNOT)
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{
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If (LGreaterEqual (\PCNT, 2)) {
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Notify (\_PR.CP00, 0x81) // _CST
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Notify (\_PR.CP01, 0x81) // _CST
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}
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If (LGreaterEqual (\PCNT, 4)) {
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Notify (\_PR.CP02, 0x81) // _CST
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Notify (\_PR.CP03, 0x81) // _CST
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}
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If (LGreaterEqual (\PCNT, 8)) {
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Notify (\_PR.CP04, 0x81) // _CST
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Notify (\_PR.CP05, 0x81) // _CST
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Notify (\_PR.CP06, 0x81) // _CST
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Notify (\_PR.CP07, 0x81) // _CST
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}
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}
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