vc/intel/fsp2_0: Add a copy of ADL-S IOT FSP MemInfoHob.h for RPL-S IOT
Similar situation happened last year when IoT FSP for ADL-S came out before the Client FSP variant: https://github.com/intel/FSP/issues/83 It seems IoT FSP publishes the MemInfoHob.h file much later due to legal reasons. Hack the missing file to get the builds using RPL-S IoT FSP from repo working properly. This change could be merged, subject for later revert (when the header file is published). Change-Id: Iec35db4573a3c3d011e4c1edf1c82a5c34438695 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This commit is contained in:
Michał Żygowski
Felix Singer
parent
12a1fc2939
commit
c651a27b53
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@ -70,6 +70,11 @@ endif
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CPPFLAGS_common += -I$(src)/soc/intel/alderlake
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CPPFLAGS_common += -I$(src)/soc/intel/alderlake/include
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# Include the missing MemInfoHob.h from vendorcode
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ifeq ($(CONFIG_SOC_INTEL_RAPTORLAKE_PCH_S)$(CONFIG_FSP_TYPE_IOT),yy)
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CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/iot/raptorlake_s
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endif
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ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_S),y)
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# 06-97-00, 06-97-01, 06-97-04 are ADL-S Engineering Samples
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# 06-97-02 are ADL-S/HX Quality Samples but also ADL-HX Engineering Samples
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@ -0,0 +1,315 @@
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/** @file
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This file contains definitions required for creation of
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Memory S3 Save data, Memory Info data and Memory Platform
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data hobs.
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@copyright
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Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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@par Specification Reference:
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**/
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#ifndef _MEM_INFO_HOB_H_
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#define _MEM_INFO_HOB_H_
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#pragma pack (push, 1)
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extern EFI_GUID gSiMemoryS3DataGuid;
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extern EFI_GUID gSiMemoryInfoDataGuid;
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extern EFI_GUID gSiMemoryPlatformDataGuid;
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#define MAX_NODE 2
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#define MAX_CH 4
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#define MAX_DIMM 2
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// Must match definitions in
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// Intel\ClientOneSiliconPkg\IpBlock\MemoryInit\Mtl\Include\MrcInterface.h
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#define HOB_MAX_SAGV_POINTS 4
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///
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/// Host reset states from MRC.
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///
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#define WARM_BOOT 2
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#define R_MC_CHNL_RANK_PRESENT 0x7C
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#define B_RANK0_PRS BIT0
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#define B_RANK1_PRS BIT1
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#define B_RANK2_PRS BIT4
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#define B_RANK3_PRS BIT5
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// @todo remove and use the MdePkg\Include\Pi\PiHob.h
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#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__)
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#ifndef __HOB__H__
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typedef struct _EFI_HOB_GENERIC_HEADER {
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UINT16 HobType;
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UINT16 HobLength;
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UINT32 Reserved;
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} EFI_HOB_GENERIC_HEADER;
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typedef struct _EFI_HOB_GUID_TYPE {
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EFI_HOB_GENERIC_HEADER Header;
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EFI_GUID Name;
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///
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/// Guid specific data goes here
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///
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} EFI_HOB_GUID_TYPE;
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#endif
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#endif
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///
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/// Defines taken from MRC so avoid having to include MrcInterface.h
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///
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//
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// Matches MAX_SPD_SAVE define in MRC
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//
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#ifndef MAX_SPD_SAVE
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#define MAX_SPD_SAVE 29
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#endif
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//
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// MRC version description.
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//
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typedef struct {
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UINT8 Major; ///< Major version number
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UINT8 Minor; ///< Minor version number
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UINT8 Rev; ///< Revision number
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UINT8 Build; ///< Build number
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} SiMrcVersion;
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//
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// Matches MrcChannelSts enum in MRC
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//
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#ifndef CHANNEL_NOT_PRESENT
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#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller.
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#endif
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#ifndef CHANNEL_DISABLED
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#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled.
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#endif
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#ifndef CHANNEL_PRESENT
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#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled.
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#endif
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//
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// Matches MrcDimmSts enum in MRC
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//
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#ifndef DIMM_ENABLED
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#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected.
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#endif
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#ifndef DIMM_DISABLED
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#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence.
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#endif
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#ifndef DIMM_PRESENT
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#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used.
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#endif
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#ifndef DIMM_NOT_PRESENT
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#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair.
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#endif
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//
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// Matches MrcBootMode enum in MRC
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//
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#ifndef __MRC_BOOT_MODE__
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#define __MRC_BOOT_MODE__ //The below values are originated from MrcCommonTypes.h
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#ifndef INT32_MAX
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#define INT32_MAX (0x7FFFFFFF)
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#endif //INT32_MAX
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typedef enum {
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bmCold, ///< Cold boot
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bmWarm, ///< Warm boot
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bmS3, ///< S3 resume
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bmFast, ///< Fast boot
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MrcBootModeMax, ///< MRC_BOOT_MODE enumeration maximum value.
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MrcBootModeDelim = INT32_MAX ///< This value ensures the enum size is consistent on both sides of the PPI.
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} MRC_BOOT_MODE;
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#endif //__MRC_BOOT_MODE__
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//
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// Matches MrcDdrType enum in MRC
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//
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#ifndef MRC_DDR_TYPE_DDR5
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#define MRC_DDR_TYPE_DDR5 1
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#endif
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#ifndef MRC_DDR_TYPE_LPDDR5
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#define MRC_DDR_TYPE_LPDDR5 2
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#endif
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#ifndef MRC_DDR_TYPE_LPDDR4
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#define MRC_DDR_TYPE_LPDDR4 3
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#endif
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#ifndef MRC_DDR_TYPE_UNKNOWN
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#define MRC_DDR_TYPE_UNKNOWN 4
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#endif
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#define MAX_PROFILE_NUM 7 // number of memory profiles supported
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#define MAX_XMP_PROFILE_NUM 5 // number of XMP profiles supported
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#define MAX_TRACE_REGION 5
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#define MAX_TRACE_CACHE_TYPE 2
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//
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// DIMM timings
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//
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typedef struct {
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UINT32 tCK; ///< Memory cycle time, in femtoseconds.
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UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode.
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UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency.
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UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
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UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
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UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
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UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
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UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
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UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
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UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.
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UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
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UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
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UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
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UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
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UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
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UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
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UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
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UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.
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UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
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UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
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UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
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UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
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} MRC_CH_TIMING;
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typedef struct {
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UINT16 tRDPRE; ///< Read CAS to Precharge cmd delay
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} MRC_IP_TIMING;
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///
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/// Memory SMBIOS & OC Memory Data Hob
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///
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typedef struct {
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UINT8 Status; ///< See MrcDimmStatus for the definition of this field.
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UINT8 DimmId;
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UINT32 DimmCapacity; ///< DIMM size in MBytes.
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UINT16 MfgId;
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UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
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UINT8 RankInDimm; ///< The number of ranks in this DIMM.
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UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
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UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
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UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
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UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
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UINT16 Speed; ///< The maximum capable speed of the device, in MHz
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UINT8 MdSocket; ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation.
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} DIMM_INFO;
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typedef struct {
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UINT8 Status; ///< Indicates whether this channel should be used.
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UINT8 ChannelId;
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UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
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MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
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DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics.
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} CHANNEL_INFO;
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typedef struct {
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UINT8 Status; ///< Indicates whether this controller should be used.
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UINT16 DeviceId; ///< The PCI device id of this memory controller.
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UINT8 RevisionId; ///< The PCI revision id of this memory controller.
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UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
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CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.
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} CONTROLLER_INFO;
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typedef struct {
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UINT64 BaseAddress; ///< Trace Base Address
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UINT64 TotalSize; ///< Total Trace Region of Same Cache type
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UINT8 CacheType; ///< Trace Cache Type
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UINT8 ErrorCode; ///< Trace Region Allocation Fail Error code
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UINT8 Rsvd[2];
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} PSMI_MEM_INFO;
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/// This data structure contains per-SaGv timing values that are considered output by the MRC.
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typedef struct {
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UINT32 DataRate; ///< The memory rate for the current SaGv Point in units of MT/s
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MRC_CH_TIMING JedecTiming; ///< Timings used for this entry's corresponding SaGv Point - derived from JEDEC SPD spec
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MRC_IP_TIMING IpTiming; ///< Timings used for this entry's corresponding SaGv Point - IP specific
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} HOB_SAGV_TIMING_OUT;
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/// This data structure contains SAGV config values that are considered output by the MRC.
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typedef struct {
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UINT32 NumSaGvPointsEnabled; ///< Count of the total number of SAGV Points enabled.
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UINT32 SaGvPointMask; ///< Bit mask where each bit indicates an enabled SAGV point.
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HOB_SAGV_TIMING_OUT SaGvTiming[HOB_MAX_SAGV_POINTS];
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} HOB_SAGV_INFO;
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typedef struct {
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UINT8 Revision;
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UINT16 DataWidth; ///< Data width, in bits, of this memory device
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/** As defined in SMBIOS 3.0 spec
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Section 7.18.2 and Table 75
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**/
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UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3
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UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)
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UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)
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/** As defined in SMBIOS 3.0 spec
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Section 7.17.3 and Table 72
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**/
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UINT8 ErrorCorrectionType;
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SiMrcVersion Version;
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BOOLEAN EccSupport;
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UINT8 MemoryProfile;
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UINT8 IsDMBRunning; ///< Deprecated.
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UINT32 TotalPhysicalMemorySize;
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UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.
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///
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/// Set of bit flags showing XMP and User Profile capability status for the DIMMs detected in system. For each bit, 1 is supported, 0 is unsupported.
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/// Bit 0: XMP Profile 1 capability status
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/// Bit 1: XMP Profile 2 capability status
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/// Bit 2: XMP Profile 3 capability status
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/// Bit 3: User Profile 4 capability status
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/// Bit 4: User Profile 5 capability status
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///
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UINT8 XmpProfileEnable;
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UINT8 XmpConfigWarning; ///< If XMP capable DIMMs config support only 1DPC, but 2DPC is installed
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UINT8 Ratio; ///< DDR Frequency Ratio, Max Value 255
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UINT8 RefClk;
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UINT32 VddVoltage[MAX_PROFILE_NUM];
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UINT32 VddqVoltage[MAX_PROFILE_NUM];
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UINT32 VppVoltage[MAX_PROFILE_NUM];
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CONTROLLER_INFO Controller[MAX_NODE];
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UINT16 Ratio_UINT16; ///< DDR Frequency Ratio, used for programs that require ratios higher then 255
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UINT32 NumPopulatedChannels; ///< Total number of memory channels populated
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HOB_SAGV_INFO SagvConfigInfo; ///< This data structure contains SAGV config values that are considered output by the MRC.
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UINT16 TotalMemWidth; ///< Total Memory Width in bits from all populated channels
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BOOLEAN MemorySpeedReducedWrongDimmSlot; ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to wrong DIMM population
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BOOLEAN MemorySpeedReducedMixedConfig; ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to mixed DIMM config
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BOOLEAN DynamicMemoryBoostTrainingFailed; ///< TRUE if Dynamic Memory Boost failed to train and was force disabled on the last full training boot. FALSE otherwise.
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} MEMORY_INFO_DATA_HOB;
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/**
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Memory Platform Data Hob
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<b>Revision 1:</b>
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- Initial version.
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<b>Revision 2:</b>
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- Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields
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**/
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typedef struct {
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UINT8 Revision;
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UINT8 Reserved[3];
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UINT32 BootMode;
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UINT32 TsegSize;
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UINT32 TsegBase;
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UINT32 PrmrrSize;
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UINT64 PrmrrBase;
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UINT32 GttBase;
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UINT32 MmioSize;
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UINT32 PciEBaseAddress;
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PSMI_MEM_INFO PsmiInfo[MAX_TRACE_CACHE_TYPE];
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PSMI_MEM_INFO PsmiRegionInfo[MAX_TRACE_REGION];
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BOOLEAN MrcBasicMemoryTestPass;
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} MEMORY_PLATFORM_DATA;
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typedef struct {
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EFI_HOB_GUID_TYPE EfiHobGuidType;
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MEMORY_PLATFORM_DATA Data;
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UINT8 *Buffer;
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} MEMORY_PLATFORM_DATA_HOB;
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#pragma pack (pop)
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#endif // _MEM_INFO_HOB_H_
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