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soc/soch/intel/tigerlake: Integrate PCIe hot-plug config UPD 

This patch adds support for enabling/disabling PCIe hot-plug via
a chip config option PcieRpHotPlug, which is copied to the corresponding
FSP-S UPD.

BUG=b:156879564
BRANCH=none
TEST=Boot Volteer/RVP with FSP log and check hotplug enabled/disabled

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I4c0187644b6ca9735f1b159e110e3466af14ff71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41794
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Wonkyu Kim 2020-05-27 13:34:04 -07:00 committed by Patrick Georgi
parent 549a853f8f
commit c66c15334a
2 changed files with 2 additions and 0 deletions
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1
src/soc/intel/tigerlake/chip.h
View File

@ -135,6 +135,7 @@ struct soc_intel_tigerlake_config {
/* PCIe Root Ports */ /* PCIe Root Ports */
uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS];
/* PCIe output clocks type to PCIe devices. /* PCIe output clocks type to PCIe devices.
* 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,
* 0xFF: not used */ * 0xFF: not used */

1
src/soc/intel/tigerlake/fsp_params.c
View File

@ -165,6 +165,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PcieRpLtrEnable[i] = config->PcieRpLtrEnable[i]; params->PcieRpLtrEnable[i] = config->PcieRpLtrEnable[i];
params->PcieRpAdvancedErrorReporting[i] = params->PcieRpAdvancedErrorReporting[i] =
config->PcieRpAdvancedErrorReporting[i]; config->PcieRpAdvancedErrorReporting[i];
params->PcieRpHotPlug[i] = config->PcieRpHotPlug[i];
} }
/* Enable ClkReqDetect for enabled port */ /* Enable ClkReqDetect for enabled port */