mb/intel/cedarisland: undo set trig and bufdis for NF pads
According to the documentation [1], RX Level/Edge Configuration (trig) and GPIO Tx/Rx Buffer Disable (bufdis) [2] settings are not applicable in native mode and BIOS does not need to configure them. Therefore, there is no need to configure this in gpio.h using PAD_CFG_NF_BUF_TRIG macros. Use PAD_CFG_NF instead and set this fields to 0. [1] Intel document #549921 [2] Intel document #336067-007US This is part of the patch set "src/mb/*, src/soc/intel/common/gpio: Remove PAD_CFG_NF_BUF_TRIG ": CB:43455 - cedarisland: undo set trig and bufdis for NF pads CB:43454 - tiogapass: undo set trig and bufdis for NF pads CB:43561 - h110m: undo set trig and bufdis for NF pads CB:43569 - soc/intel/common/gpio_defs: Remove PAD_CFG_NF_BUF_TRIG Change-Id: Ie3ee2eadc08826d49e8517c83ab6831398e3aa93 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43455 Reviewed-by: Michael Niewöhner Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Maxim Polyakov
Michael Niewöhner
parent
a81c8ee3a1
commit
c685607e4d
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@ -10,27 +10,27 @@ static const struct pad_config gpio_table[] = {
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/* ------- GPIO Community 0 ------- */
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/* ------- GPIO Community 0 ------- */
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/* ------- GPIO Group GPP_A ------- */
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/* ------- GPIO Group GPP_A ------- */
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/* GPP_A0 - ESPI_ALERT1# */
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/* GPP_A0 - ESPI_ALERT1# */
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PAD_CFG_NF_BUF_TRIG(GPP_A0, NONE, DEEP, NF3, TX_DISABLE, OFF),
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PAD_CFG_NF(GPP_A0, NONE, DEEP, NF3),
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/* GPP_A1 - ESPI_IO0 */
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/* GPP_A1 - ESPI_IO0 */
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PAD_CFG_NF_BUF_TRIG(GPP_A1, 20K_PU, DEEP, NF3, NO_DISABLE, OFF),
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PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF3),
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/* GPP_A2 - ESPI_IO1 */
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/* GPP_A2 - ESPI_IO1 */
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PAD_CFG_NF_BUF_TRIG(GPP_A2, 20K_PU, DEEP, NF3, NO_DISABLE, OFF),
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PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF3),
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/* GPP_A3 - ESPI_IO2 */
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/* GPP_A3 - ESPI_IO2 */
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PAD_CFG_NF_BUF_TRIG(GPP_A3, 20K_PU, DEEP, NF3, NO_DISABLE, OFF),
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PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF3),
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/* GPP_A4 - ESPI_IO3 */
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/* GPP_A4 - ESPI_IO3 */
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PAD_CFG_NF_BUF_TRIG(GPP_A4, 20K_PU, DEEP, NF3, NO_DISABLE, OFF),
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PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF3),
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/* GPP_A5 - ESPI_CS0# */
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/* GPP_A5 - ESPI_CS0# */
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PAD_CFG_NF_BUF_TRIG(GPP_A5, 20K_PU, DEEP, NF3, RX_DISABLE, OFF),
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PAD_CFG_NF(GPP_A5, 20K_PU, DEEP, NF3),
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/* GPP_A6 - ESPI_CS1# */
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/* GPP_A6 - ESPI_CS1# */
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PAD_CFG_NF_BUF_TRIG(GPP_A6, NONE, DEEP, NF3, RX_DISABLE, OFF),
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PAD_CFG_NF(GPP_A6, NONE, DEEP, NF3),
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/* GPP_A7 - ESPI_ALERT0# */
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/* GPP_A7 - ESPI_ALERT0# */
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PAD_CFG_NF_BUF_TRIG(GPP_A7, NONE, DEEP, NF3, TX_DISABLE, OFF),
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PAD_CFG_NF(GPP_A7, NONE, DEEP, NF3),
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/* GPP_A8 - CLKRUN# */
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/* GPP_A8 - CLKRUN# */
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PAD_CFG_NF_BUF_TRIG(GPP_A8, NONE, DEEP, NF1, NO_DISABLE, OFF),
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PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
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/* GPP_A9 - ESPI_CLK */
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/* GPP_A9 - ESPI_CLK */
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PAD_CFG_NF_BUF_TRIG(GPP_A9, 20K_PD, DEEP, NF3, RX_DISABLE, OFF),
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PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF3),
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/* GPP_A10 - CLKOUT_LPC1 */
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/* GPP_A10 - CLKOUT_LPC1 */
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PAD_CFG_NF_BUF_TRIG(GPP_A10, NONE, DEEP, NF1, TX_DISABLE, OFF),
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PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
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/* GPP_A11 - GPIO */
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/* GPP_A11 - GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPP_A11, NONE, DEEP, OFF, DRIVER),
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PAD_CFG_GPI_TRIG_OWN(GPP_A11, NONE, DEEP, OFF, DRIVER),
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/* GPP_A12 - GPIO */
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/* GPP_A12 - GPIO */
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@ -38,7 +38,7 @@ static const struct pad_config gpio_table[] = {
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/* GPP_A13 - GPIO */
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/* GPP_A13 - GPIO */
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PAD_CFG_GPO(GPP_A13, 0, DEEP),
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PAD_CFG_GPO(GPP_A13, 0, DEEP),
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/* GPP_A14 - ESPI_RESET# */
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/* GPP_A14 - ESPI_RESET# */
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PAD_CFG_NF_BUF_TRIG(GPP_A14, NONE, DEEP, NF3, RX_DISABLE, OFF),
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PAD_CFG_NF(GPP_A14, NONE, DEEP, NF3),
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/* GPP_A15 - GPIO */
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/* GPP_A15 - GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPP_A15, NONE, DEEP, OFF, DRIVER),
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PAD_CFG_GPI_TRIG_OWN(GPP_A15, NONE, DEEP, OFF, DRIVER),
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/* GPP_A16 - GPIO */
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/* GPP_A16 - GPIO */
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@ -59,9 +59,9 @@ static const struct pad_config gpio_table[] = {
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/* ------- GPIO Group GPP_B ------- */
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/* ------- GPIO Group GPP_B ------- */
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/* GPP_B0 - CORE_VID0 */
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/* GPP_B0 - CORE_VID0 */
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PAD_CFG_NF_BUF_TRIG(GPP_B0, NONE, RSMRST, NF1, RX_DISABLE, OFF),
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PAD_CFG_NF(GPP_B0, NONE, RSMRST, NF1),
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/* GPP_B1 - CORE_VID1 */
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/* GPP_B1 - CORE_VID1 */
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PAD_CFG_NF_BUF_TRIG(GPP_B1, NONE, RSMRST, NF1, RX_DISABLE, OFF),
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PAD_CFG_NF(GPP_B1, NONE, RSMRST, NF1),
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/* GPP_B2 - GPIO */
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/* GPP_B2 - GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPP_B2, NONE, RSMRST, OFF, ACPI),
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PAD_CFG_GPI_TRIG_OWN(GPP_B2, NONE, RSMRST, OFF, ACPI),
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/* GPP_B3 - GPIO */
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/* GPP_B3 - GPIO */
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@ -84,9 +84,9 @@ static const struct pad_config gpio_table[] = {
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/* GPP_B12 - GPIO */
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/* GPP_B12 - GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPP_B12, NONE, RSMRST, OFF, ACPI),
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PAD_CFG_GPI_TRIG_OWN(GPP_B12, NONE, RSMRST, OFF, ACPI),
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/* GPP_B13 - PLTRST# */
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/* GPP_B13 - PLTRST# */
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PAD_CFG_NF_BUF_TRIG(GPP_B13, NONE, RSMRST, NF1, RX_DISABLE, OFF),
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PAD_CFG_NF(GPP_B13, NONE, RSMRST, NF1),
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/* GPP_B14 - SPKR */
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/* GPP_B14 - SPKR */
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PAD_CFG_NF_BUF_TRIG(GPP_B14, NONE, RSMRST, NF1, TX_DISABLE, OFF),
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PAD_CFG_NF(GPP_B14, NONE, RSMRST, NF1),
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/* GPP_B15 - GPIO */
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/* GPP_B15 - GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPP_B15, NONE, RSMRST, OFF, ACPI),
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PAD_CFG_GPI_TRIG_OWN(GPP_B15, NONE, RSMRST, OFF, ACPI),
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/* GPP_B16 - GPIO */
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/* GPP_B16 - GPIO */
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@ -104,19 +104,19 @@ static const struct pad_config gpio_table[] = {
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/* GPP_B22 - GPIO */
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/* GPP_B22 - GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPP_B22, NONE, RSMRST, OFF, ACPI),
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PAD_CFG_GPI_TRIG_OWN(GPP_B22, NONE, RSMRST, OFF, ACPI),
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/* GPP_B23 - PCHHOT# */
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/* GPP_B23 - PCHHOT# */
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PAD_CFG_NF_BUF_TRIG(GPP_B23, NONE, RSMRST, NF2, RX_DISABLE, OFF),
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PAD_CFG_NF(GPP_B23, NONE, RSMRST, NF2),
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/* ------- GPIO Group GPP_F ------- */
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/* ------- GPIO Group GPP_F ------- */
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/* GPP_F0 - SATAXPCIE3 */
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/* GPP_F0 - SATAXPCIE3 */
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PAD_CFG_NF_BUF_TRIG(GPP_F0, NONE, RSMRST, NF1, TX_DISABLE, OFF),
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PAD_CFG_NF(GPP_F0, NONE, RSMRST, NF1),
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/* GPP_F1 - SATAXPCIE4 */
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/* GPP_F1 - SATAXPCIE4 */
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PAD_CFG_NF_BUF_TRIG(GPP_F1, NONE, RSMRST, NF1, TX_DISABLE, OFF),
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PAD_CFG_NF(GPP_F1, NONE, RSMRST, NF1),
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/* GPP_F2 - SATAXPCIE5 */
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/* GPP_F2 - SATAXPCIE5 */
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PAD_CFG_NF_BUF_TRIG(GPP_F2, NONE, RSMRST, NF1, TX_DISABLE, OFF),
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PAD_CFG_NF(GPP_F2, NONE, RSMRST, NF1),
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/* GPP_F3 - SATAXPCIE6 */
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/* GPP_F3 - SATAXPCIE6 */
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PAD_CFG_NF_BUF_TRIG(GPP_F3, NONE, RSMRST, NF1, TX_DISABLE, OFF),
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PAD_CFG_NF(GPP_F3, NONE, RSMRST, NF1),
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/* GPP_F4 - SATAXPCIE7 */
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/* GPP_F4 - SATAXPCIE7 */
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PAD_CFG_NF_BUF_TRIG(GPP_F4, NONE, RSMRST, NF1, TX_DISABLE, OFF),
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PAD_CFG_NF(GPP_F4, NONE, RSMRST, NF1),
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/* GPP_F5 - GPIO */
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/* GPP_F5 - GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPP_F5, NONE, RSMRST, OFF, ACPI),
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PAD_CFG_GPI_TRIG_OWN(GPP_F5, NONE, RSMRST, OFF, ACPI),
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/* GPP_F6 - GPIO */
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/* GPP_F6 - GPIO */
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@ -128,33 +128,33 @@ static const struct pad_config gpio_table[] = {
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/* GPP_F9 - GPIO */
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/* GPP_F9 - GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPP_F9, NONE, RSMRST, OFF, ACPI),
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PAD_CFG_GPI_TRIG_OWN(GPP_F9, NONE, RSMRST, OFF, ACPI),
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/* GPP_F10 - SATA_SCLOCK */
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/* GPP_F10 - SATA_SCLOCK */
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PAD_CFG_NF_BUF_TRIG(GPP_F10, NONE, RSMRST, NF1, RX_DISABLE, OFF),
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PAD_CFG_NF(GPP_F10, NONE, RSMRST, NF1),
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/* GPP_F11 - SATA_SLOAD */
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/* GPP_F11 - SATA_SLOAD */
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PAD_CFG_NF_BUF_TRIG(GPP_F11, NONE, RSMRST, NF1, RX_DISABLE, OFF),
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PAD_CFG_NF(GPP_F11, NONE, RSMRST, NF1),
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/* GPP_F12 - SATA_SDATAOUT1 */
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/* GPP_F12 - SATA_SDATAOUT1 */
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PAD_CFG_NF_BUF_TRIG(GPP_F12, NONE, RSMRST, NF1, RX_DISABLE, OFF),
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PAD_CFG_NF(GPP_F12, NONE, RSMRST, NF1),
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/* GPP_F13 - SATA_SDATAOUT2 */
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/* GPP_F13 - SATA_SDATAOUT2 */
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PAD_CFG_NF_BUF_TRIG(GPP_F13, NONE, RSMRST, NF1, RX_DISABLE, OFF),
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PAD_CFG_NF(GPP_F13, NONE, RSMRST, NF1),
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/* GPP_F14 - SSATA_LED# */
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/* GPP_F14 - SSATA_LED# */
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PAD_CFG_NF_BUF_TRIG(GPP_F14, NONE, RSMRST, NF3, RX_DISABLE, OFF),
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PAD_CFG_NF(GPP_F14, NONE, RSMRST, NF3),
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/* GPP_F15 - USB_OC4# */
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/* GPP_F15 - USB_OC4# */
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PAD_CFG_NF_BUF_TRIG(GPP_F15, NONE, RSMRST, NF1, TX_DISABLE, OFF),
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PAD_CFG_NF(GPP_F15, NONE, RSMRST, NF1),
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/* GPP_F16 - USB_OC5# */
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/* GPP_F16 - USB_OC5# */
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PAD_CFG_NF_BUF_TRIG(GPP_F16, NONE, RSMRST, NF1, TX_DISABLE, OFF),
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PAD_CFG_NF(GPP_F16, NONE, RSMRST, NF1),
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/* GPP_F17 - USB_OC6# */
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/* GPP_F17 - USB_OC6# */
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PAD_CFG_NF_BUF_TRIG(GPP_F17, NONE, RSMRST, NF1, TX_DISABLE, OFF),
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PAD_CFG_NF(GPP_F17, NONE, RSMRST, NF1),
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/* GPP_F18 - USB_OC7# */
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/* GPP_F18 - USB_OC7# */
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PAD_CFG_NF_BUF_TRIG(GPP_F18, NONE, RSMRST, NF1, TX_DISABLE, OFF),
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PAD_CFG_NF(GPP_F18, NONE, RSMRST, NF1),
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/* GPP_F19 - LAN_SMBCLK */
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/* GPP_F19 - LAN_SMBCLK */
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PAD_CFG_NF_BUF_TRIG(GPP_F19, NONE, RSMRST, NF1, NO_DISABLE, OFF),
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PAD_CFG_NF(GPP_F19, NONE, RSMRST, NF1),
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/* GPP_F20 - LAN_SMBDATA */
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/* GPP_F20 - LAN_SMBDATA */
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PAD_CFG_NF_BUF_TRIG(GPP_F20, NONE, RSMRST, NF1, NO_DISABLE, OFF),
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PAD_CFG_NF(GPP_F20, NONE, RSMRST, NF1),
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/* GPP_F21 - GPIO */
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/* GPP_F21 - GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPP_F21, NONE, RSMRST, OFF, ACPI),
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PAD_CFG_GPI_TRIG_OWN(GPP_F21, NONE, RSMRST, OFF, ACPI),
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/* GPP_F22 - SSATA_SCLOCK */
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/* GPP_F22 - SSATA_SCLOCK */
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PAD_CFG_NF_BUF_TRIG(GPP_F22, NONE, RSMRST, NF3, RX_DISABLE, OFF),
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PAD_CFG_NF(GPP_F22, NONE, RSMRST, NF3),
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/* GPP_F23 - SSATA_SLOAD */
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/* GPP_F23 - SSATA_SLOAD */
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PAD_CFG_NF_BUF_TRIG(GPP_F23, NONE, RSMRST, NF3, RX_DISABLE, OFF),
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PAD_CFG_NF(GPP_F23, NONE, RSMRST, NF3),
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/* ------- GPIO Community 1 ------- */
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/* ------- GPIO Community 1 ------- */
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/* ------- GPIO Group GPP_C ------- */
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/* ------- GPIO Group GPP_C ------- */
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@ -165,7 +165,7 @@ static const struct pad_config gpio_table[] = {
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/* GPP_C3 - RESERVED */
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/* GPP_C3 - RESERVED */
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/* GPP_C4 - RESERVED */
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/* GPP_C4 - RESERVED */
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/* GPP_C5 - SML0ALERT# */
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/* GPP_C5 - SML0ALERT# */
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PAD_CFG_NF_BUF_TRIG(GPP_C5, NONE, RSMRST, NF1, RX_DISABLE, OFF),
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PAD_CFG_NF(GPP_C5, NONE, RSMRST, NF1),
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/* GPP_C6 - RESERVED */
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/* GPP_C6 - RESERVED */
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/* GPP_C7 - RESERVED */
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/* GPP_C7 - RESERVED */
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/* GPP_C8 - GPIO */
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/* GPP_C8 - GPIO */
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@ -225,17 +225,17 @@ static const struct pad_config gpio_table[] = {
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/* GPP_D9 - GPIO */
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/* GPP_D9 - GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPP_D9, NONE, RSMRST, OFF, ACPI),
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PAD_CFG_GPI_TRIG_OWN(GPP_D9, NONE, RSMRST, OFF, ACPI),
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/* GPP_D10 - SSATA_DEVSLP4 */
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/* GPP_D10 - SSATA_DEVSLP4 */
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PAD_CFG_NF_BUF_TRIG(GPP_D10, NONE, RSMRST, NF3, RX_DISABLE, OFF),
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PAD_CFG_NF(GPP_D10, NONE, RSMRST, NF3),
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/* GPP_D11 - GPIO */
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/* GPP_D11 - GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPP_D11, NONE, RSMRST, OFF, ACPI),
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PAD_CFG_GPI_TRIG_OWN(GPP_D11, NONE, RSMRST, OFF, ACPI),
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/* GPP_D12 - SSATA_SDATAOUT1 */
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/* GPP_D12 - SSATA_SDATAOUT1 */
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PAD_CFG_NF_BUF_TRIG(GPP_D12, NONE, RSMRST, NF3, RX_DISABLE, OFF),
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PAD_CFG_NF(GPP_D12, NONE, RSMRST, NF3),
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/* GPP_D13 - SML0BCLK_IE */
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/* GPP_D13 - SML0BCLK_IE */
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PAD_CFG_NF_BUF_TRIG(GPP_D13, NONE, RSMRST, NF3, NO_DISABLE, OFF),
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PAD_CFG_NF(GPP_D13, NONE, RSMRST, NF3),
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/* GPP_D14 - SML0BDATA_IE */
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/* GPP_D14 - SML0BDATA_IE */
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PAD_CFG_NF_BUF_TRIG(GPP_D14, NONE, RSMRST, NF3, NO_DISABLE, OFF),
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PAD_CFG_NF(GPP_D14, NONE, RSMRST, NF3),
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/* GPP_D15 - SSATA_SDATAOUT0 */
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/* GPP_D15 - SSATA_SDATAOUT0 */
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PAD_CFG_NF_BUF_TRIG(GPP_D15, NONE, RSMRST, NF3, RX_DISABLE, OFF),
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PAD_CFG_NF(GPP_D15, NONE, RSMRST, NF3),
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/* GPP_D16 - GPIO */
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/* GPP_D16 - GPIO */
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PAD_CFG_GPO(GPP_D16, 0, RSMRST),
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PAD_CFG_GPO(GPP_D16, 0, RSMRST),
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/* GPP_D17 - GPIO */
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/* GPP_D17 - GPIO */
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@ -255,13 +255,13 @@ static const struct pad_config gpio_table[] = {
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/* ------- GPIO Group GPP_E ------- */
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/* ------- GPIO Group GPP_E ------- */
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/* GPP_E0 - SATAXPCIE0 */
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/* GPP_E0 - SATAXPCIE0 */
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PAD_CFG_NF_BUF_TRIG(GPP_E0, NONE, RSMRST, NF1, TX_DISABLE, OFF),
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PAD_CFG_NF(GPP_E0, NONE, RSMRST, NF1),
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/* GPP_E1 - SATAXPCIE1 */
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/* GPP_E1 - SATAXPCIE1 */
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PAD_CFG_NF_BUF_TRIG(GPP_E1, NONE, RSMRST, NF1, TX_DISABLE, OFF),
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PAD_CFG_NF(GPP_E1, NONE, RSMRST, NF1),
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/* GPP_E2 - SATAXPCIE2 */
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/* GPP_E2 - SATAXPCIE2 */
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PAD_CFG_NF_BUF_TRIG(GPP_E2, NONE, RSMRST, NF1, TX_DISABLE, OFF),
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PAD_CFG_NF(GPP_E2, NONE, RSMRST, NF1),
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/* GPP_E3 - CPU_GP0 */
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/* GPP_E3 - CPU_GP0 */
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PAD_CFG_NF_BUF_TRIG(GPP_E3, NONE, RSMRST, NF1, TX_DISABLE, OFF),
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PAD_CFG_NF(GPP_E3, NONE, RSMRST, NF1),
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/* GPP_E4 - GPIO */
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/* GPP_E4 - GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPP_E4, NONE, RSMRST, OFF, ACPI),
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PAD_CFG_GPI_TRIG_OWN(GPP_E4, NONE, RSMRST, OFF, ACPI),
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/* GPP_E5 - GPIO */
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/* GPP_E5 - GPIO */
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@ -271,31 +271,31 @@ static const struct pad_config gpio_table[] = {
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/* GPP_E7 - GPIO */
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/* GPP_E7 - GPIO */
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PAD_CFG_GPI_SMI(GPP_E7, NONE, DEEP, LEVEL, INVERT),
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PAD_CFG_GPI_SMI(GPP_E7, NONE, DEEP, LEVEL, INVERT),
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/* GPP_E8 - SATA_LED# */
|
/* GPP_E8 - SATA_LED# */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_E8, NONE, RSMRST, NF1, RX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_E8, NONE, RSMRST, NF1),
|
||||||
/* GPP_E9 - USB_OC0# */
|
/* GPP_E9 - USB_OC0# */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_E9, NONE, RSMRST, NF1, TX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_E9, NONE, RSMRST, NF1),
|
||||||
/* GPP_E10 - USB_OC1# */
|
/* GPP_E10 - USB_OC1# */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_E10, NONE, RSMRST, NF1, TX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_E10, NONE, RSMRST, NF1),
|
||||||
/* GPP_E11 - USB_OC2# */
|
/* GPP_E11 - USB_OC2# */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_E11, NONE, RSMRST, NF1, TX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_E11, NONE, RSMRST, NF1),
|
||||||
/* GPP_E12 - USB_OC3# */
|
/* GPP_E12 - USB_OC3# */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_E12, NONE, RSMRST, NF1, TX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_E12, NONE, RSMRST, NF1),
|
||||||
|
|
||||||
/* ------- GPIO Community 2 ------- */
|
/* ------- GPIO Community 2 ------- */
|
||||||
/* -------- GPIO Group GPD -------- */
|
/* -------- GPIO Group GPD -------- */
|
||||||
/* GPD0 - RESERVED */
|
/* GPD0 - RESERVED */
|
||||||
/* GPD1 - ACPRESENT */
|
/* GPD1 - ACPRESENT */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPD1, NONE, RSMRST, NF1, TX_DISABLE, OFF),
|
PAD_CFG_NF(GPD1, NONE, RSMRST, NF1),
|
||||||
/* GPD2 - GBE_WAKE# */
|
/* GPD2 - GBE_WAKE# */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPD2, NONE, RSMRST, NF1, TX_DISABLE, OFF),
|
PAD_CFG_NF(GPD2, NONE, RSMRST, NF1),
|
||||||
/* GPD3 - PWRBTN# */
|
/* GPD3 - PWRBTN# */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPD3, NONE, RSMRST, NF1, TX_DISABLE, OFF),
|
PAD_CFG_NF(GPD3, NONE, RSMRST, NF1),
|
||||||
/* GPD4 - SLP_S3# */
|
/* GPD4 - SLP_S3# */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPD4, NONE, RSMRST, NF1, RX_DISABLE, OFF),
|
PAD_CFG_NF(GPD4, NONE, RSMRST, NF1),
|
||||||
/* GPD5 - SLP_S4# */
|
/* GPD5 - SLP_S4# */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPD5, NONE, RSMRST, NF1, RX_DISABLE, OFF),
|
PAD_CFG_NF(GPD5, NONE, RSMRST, NF1),
|
||||||
/* GPD6 - SLP_A# */
|
/* GPD6 - SLP_A# */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPD6, NONE, RSMRST, NF1, RX_DISABLE, OFF),
|
PAD_CFG_NF(GPD6, NONE, RSMRST, NF1),
|
||||||
/* GPD7 - GPIO */
|
/* GPD7 - GPIO */
|
||||||
PAD_CFG_GPI_TRIG_OWN(GPD7, NONE, RSMRST, OFF, ACPI),
|
PAD_CFG_GPI_TRIG_OWN(GPD7, NONE, RSMRST, OFF, ACPI),
|
||||||
/* GPD8 - GPIO */
|
/* GPD8 - GPIO */
|
||||||
|
|
@ -303,20 +303,20 @@ static const struct pad_config gpio_table[] = {
|
||||||
/* GPD9 - GPIO */
|
/* GPD9 - GPIO */
|
||||||
PAD_CFG_GPI_TRIG_OWN(GPD9, NONE, RSMRST, OFF, ACPI),
|
PAD_CFG_GPI_TRIG_OWN(GPD9, NONE, RSMRST, OFF, ACPI),
|
||||||
/* GPD10 - SLP_S5# */
|
/* GPD10 - SLP_S5# */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPD10, NONE, RSMRST, NF1, RX_DISABLE, OFF),
|
PAD_CFG_NF(GPD10, NONE, RSMRST, NF1),
|
||||||
/* GPD11 - GBEPHY */
|
/* GPD11 - GBEPHY */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPD11, NONE, RSMRST, NF1, RX_DISABLE, OFF),
|
PAD_CFG_NF(GPD11, NONE, RSMRST, NF1),
|
||||||
|
|
||||||
/* ------- GPIO Community 3 ------- */
|
/* ------- GPIO Community 3 ------- */
|
||||||
/* ------- GPIO Group GPP_I ------- */
|
/* ------- GPIO Group GPP_I ------- */
|
||||||
/* GPP_I0 - LAN_TDO */
|
/* GPP_I0 - LAN_TDO */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_I0, NONE, RSMRST, NF2, RX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_I0, NONE, RSMRST, NF2),
|
||||||
/* GPP_I1 - LAN_TCK */
|
/* GPP_I1 - LAN_TCK */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_I1, NONE, RSMRST, NF2, TX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_I1, NONE, RSMRST, NF2),
|
||||||
/* GPP_I2 - LAN_TMS */
|
/* GPP_I2 - LAN_TMS */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_I2, NONE, RSMRST, NF2, TX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_I2, NONE, RSMRST, NF2),
|
||||||
/* GPP_I3 - LAN_TDI */
|
/* GPP_I3 - LAN_TDI */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_I3, NONE, RSMRST, NF2, TX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_I3, NONE, RSMRST, NF2),
|
||||||
/* GPP_I4 - GPIO */
|
/* GPP_I4 - GPIO */
|
||||||
_PAD_CFG_STRUCT(GPP_I4,
|
_PAD_CFG_STRUCT(GPP_I4,
|
||||||
PAD_FUNC(GPIO) | PAD_RESET(RSMRST) |
|
PAD_FUNC(GPIO) | PAD_RESET(RSMRST) |
|
||||||
|
|
@ -327,11 +327,11 @@ static const struct pad_config gpio_table[] = {
|
||||||
/* GPP_I6 - GPIO */
|
/* GPP_I6 - GPIO */
|
||||||
PAD_CFG_GPI_TRIG_OWN(GPP_I6, NONE, RSMRST, OFF, ACPI),
|
PAD_CFG_GPI_TRIG_OWN(GPP_I6, NONE, RSMRST, OFF, ACPI),
|
||||||
/* GPP_I7 - LAN_TRST_IN */
|
/* GPP_I7 - LAN_TRST_IN */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_I7, NONE, RSMRST, NF2, TX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_I7, NONE, RSMRST, NF2),
|
||||||
/* GPP_I8 - PCI_DIS */
|
/* GPP_I8 - PCI_DIS */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_I8, NONE, RSMRST, NF2, TX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_I8, NONE, RSMRST, NF2),
|
||||||
/* GPP_I9 - LAN_DIS */
|
/* GPP_I9 - LAN_DIS */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_I9, NONE, RSMRST, NF2, TX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_I9, NONE, RSMRST, NF2),
|
||||||
/* GPP_I10 - GPIO */
|
/* GPP_I10 - GPIO */
|
||||||
PAD_CFG_GPI_TRIG_OWN(GPP_I10, NONE, RSMRST, OFF, ACPI),
|
PAD_CFG_GPI_TRIG_OWN(GPP_I10, NONE, RSMRST, OFF, ACPI),
|
||||||
|
|
||||||
|
|
@ -394,27 +394,27 @@ static const struct pad_config gpio_table[] = {
|
||||||
|
|
||||||
/* ------- GPIO Group GPP_K ------- */
|
/* ------- GPIO Group GPP_K ------- */
|
||||||
/* GPP_K0 - LAN_NCSI_CLK_IN */
|
/* GPP_K0 - LAN_NCSI_CLK_IN */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_K0, NONE, RSMRST, NF1, NO_DISABLE, OFF),
|
PAD_CFG_NF(GPP_K0, NONE, RSMRST, NF1),
|
||||||
/* GPP_K1 - LAN_NCSI_TXD0 */
|
/* GPP_K1 - LAN_NCSI_TXD0 */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_K1, NONE, RSMRST, NF1, TX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_K1, NONE, RSMRST, NF1),
|
||||||
/* GPP_K2 - LAN_NCSI_TXD1 */
|
/* GPP_K2 - LAN_NCSI_TXD1 */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_K2, NONE, RSMRST, NF1, TX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_K2, NONE, RSMRST, NF1),
|
||||||
/* GPP_K3 - LAN_NCSI_TX_EN */
|
/* GPP_K3 - LAN_NCSI_TX_EN */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_K3, NONE, RSMRST, NF1, TX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_K3, NONE, RSMRST, NF1),
|
||||||
/* GPP_K4 - LAN_NCSI_CRS_DV */
|
/* GPP_K4 - LAN_NCSI_CRS_DV */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_K4, NONE, RSMRST, NF1, RX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_K4, NONE, RSMRST, NF1),
|
||||||
/* GPP_K5 - LAN_NCSI_RXD0 */
|
/* GPP_K5 - LAN_NCSI_RXD0 */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_K5, NONE, RSMRST, NF1, TX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_K5, NONE, RSMRST, NF1),
|
||||||
/* GPP_K6 - LAN_NCSI_RXD1 */
|
/* GPP_K6 - LAN_NCSI_RXD1 */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_K6, NONE, RSMRST, NF1, TX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_K6, NONE, RSMRST, NF1),
|
||||||
/* GPP_K7 - RESERVED */
|
/* GPP_K7 - RESERVED */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_K7, NONE, RSMRST, NF1, NO_DISABLE, OFF),
|
PAD_CFG_NF(GPP_K7, NONE, RSMRST, NF1),
|
||||||
/* GPP_K8 - LAN_NCSI_ARB_IN */
|
/* GPP_K8 - LAN_NCSI_ARB_IN */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_K8, NONE, RSMRST, NF1, TX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_K8, NONE, RSMRST, NF1),
|
||||||
/* GPP_K9 - LAN_NCSI_ARB_OUT */
|
/* GPP_K9 - LAN_NCSI_ARB_OUT */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_K9, NONE, RSMRST, NF1, RX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_K9, NONE, RSMRST, NF1),
|
||||||
/* GPP_K10 - PE_RST# */
|
/* GPP_K10 - PE_RST# */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_K10, NONE, RSMRST, NF1, TX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_K10, NONE, RSMRST, NF1),
|
||||||
|
|
||||||
/* ------- GPIO Community 5 ------- */
|
/* ------- GPIO Community 5 ------- */
|
||||||
/* ------- GPIO Group GPP_G ------- */
|
/* ------- GPIO Group GPP_G ------- */
|
||||||
|
|
@ -453,16 +453,16 @@ static const struct pad_config gpio_table[] = {
|
||||||
/* GPP_G16 - GPIO */
|
/* GPP_G16 - GPIO */
|
||||||
PAD_CFG_GPI_TRIG_OWN(GPP_G16, NONE, RSMRST, OFF, ACPI),
|
PAD_CFG_GPI_TRIG_OWN(GPP_G16, NONE, RSMRST, OFF, ACPI),
|
||||||
/* GPP_G17 - ADR_COMPLETE */
|
/* GPP_G17 - ADR_COMPLETE */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_G17, NONE, RSMRST, NF1, RX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_G17, NONE, RSMRST, NF1),
|
||||||
/* GPP_G18 - NMI# */
|
/* GPP_G18 - NMI# */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_G18, NONE, RSMRST, NF1, RX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_G18, NONE, RSMRST, NF1),
|
||||||
/* GPP_G19 - SMI# */
|
/* GPP_G19 - SMI# */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_G19, NONE, RSMRST, NF1, RX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_G19, NONE, RSMRST, NF1),
|
||||||
/* GPP_G20 - RESERVED */
|
/* GPP_G20 - RESERVED */
|
||||||
/* GPP_G21 - GPIO */
|
/* GPP_G21 - GPIO */
|
||||||
PAD_CFG_GPI_TRIG_OWN(GPP_G21, NONE, RSMRST, OFF, ACPI),
|
PAD_CFG_GPI_TRIG_OWN(GPP_G21, NONE, RSMRST, OFF, ACPI),
|
||||||
/* GPP_G22 - n/a */
|
/* GPP_G22 - n/a */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_G22, NONE, RSMRST, NF3, RX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_G22, NONE, RSMRST, NF3),
|
||||||
/* GPP_G23 - GPIO */
|
/* GPP_G23 - GPIO */
|
||||||
PAD_CFG_GPI_TRIG_OWN(GPP_G23, NONE, RSMRST, OFF, ACPI),
|
PAD_CFG_GPI_TRIG_OWN(GPP_G23, NONE, RSMRST, OFF, ACPI),
|
||||||
|
|
||||||
|
|
@ -491,14 +491,14 @@ static const struct pad_config gpio_table[] = {
|
||||||
PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)),
|
PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)),
|
||||||
/* GPP_H5 - RESERVED */
|
/* GPP_H5 - RESERVED */
|
||||||
/* GPP_H6 - SRCCLKREQ12# */
|
/* GPP_H6 - SRCCLKREQ12# */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_H6, NONE, RSMRST, NF1, TX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_H6, NONE, RSMRST, NF1),
|
||||||
/* GPP_H7 - GPIO */
|
/* GPP_H7 - GPIO */
|
||||||
_PAD_CFG_STRUCT(GPP_H7,
|
_PAD_CFG_STRUCT(GPP_H7,
|
||||||
PAD_FUNC(GPIO) | PAD_RESET(RSMRST) |
|
PAD_FUNC(GPIO) | PAD_RESET(RSMRST) |
|
||||||
PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE),
|
PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE),
|
||||||
PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)),
|
PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)),
|
||||||
/* GPP_H8 - SRCCLKREQ14# */
|
/* GPP_H8 - SRCCLKREQ14# */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_H8, NONE, RSMRST, NF1, TX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_H8, NONE, RSMRST, NF1),
|
||||||
/* GPP_H9 - GPIO */
|
/* GPP_H9 - GPIO */
|
||||||
_PAD_CFG_STRUCT(GPP_H9,
|
_PAD_CFG_STRUCT(GPP_H9,
|
||||||
PAD_FUNC(GPIO) | PAD_RESET(RSMRST) |
|
PAD_FUNC(GPIO) | PAD_RESET(RSMRST) |
|
||||||
|
|
@ -519,54 +519,54 @@ static const struct pad_config gpio_table[] = {
|
||||||
/* GPP_H19 - GPIO */
|
/* GPP_H19 - GPIO */
|
||||||
PAD_CFG_GPO(GPP_H19, 0, RSMRST),
|
PAD_CFG_GPO(GPP_H19, 0, RSMRST),
|
||||||
/* GPP_H20 - SSATAXPCIE2 */
|
/* GPP_H20 - SSATAXPCIE2 */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_H20, NONE, RSMRST, NF2, TX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_H20, NONE, RSMRST, NF2),
|
||||||
/* GPP_H21 - GPIO */
|
/* GPP_H21 - GPIO */
|
||||||
PAD_CFG_GPO(GPP_H21, 0, RSMRST),
|
PAD_CFG_GPO(GPP_H21, 0, RSMRST),
|
||||||
/* GPP_H22 - SSATAXPCIE4 */
|
/* GPP_H22 - SSATAXPCIE4 */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_H22, NONE, RSMRST, NF2, TX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_H22, NONE, RSMRST, NF2),
|
||||||
/* GPP_H23 - GPIO */
|
/* GPP_H23 - GPIO */
|
||||||
PAD_CFG_GPI_TRIG_OWN(GPP_H23, NONE, RSMRST, OFF, ACPI),
|
PAD_CFG_GPI_TRIG_OWN(GPP_H23, NONE, RSMRST, OFF, ACPI),
|
||||||
|
|
||||||
/* ------- GPIO Group GPP_L ------- */
|
/* ------- GPIO Group GPP_L ------- */
|
||||||
/* GPP_L0 - RESERVED */
|
/* GPP_L0 - RESERVED */
|
||||||
/* GPP_L1 - CSME_INTR_OUT */
|
/* GPP_L1 - CSME_INTR_OUT */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_L1, NONE, DEEP, NF1, TX_RX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_L1, NONE, DEEP, NF1),
|
||||||
/* GPP_L2 - TESTCH0_D0 */
|
/* GPP_L2 - TESTCH0_D0 */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_L2, NONE, RSMRST, NF1, RX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_L2, NONE, RSMRST, NF1),
|
||||||
/* GPP_L3 - TESTCH0_D1 */
|
/* GPP_L3 - TESTCH0_D1 */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_L3, NONE, RSMRST, NF1, RX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_L3, NONE, RSMRST, NF1),
|
||||||
/* GPP_L4 - TESTCH0_D2 */
|
/* GPP_L4 - TESTCH0_D2 */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_L4, NONE, RSMRST, NF1, RX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_L4, NONE, RSMRST, NF1),
|
||||||
/* GPP_L5 - TESTCH0_D3 */
|
/* GPP_L5 - TESTCH0_D3 */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_L5, NONE, RSMRST, NF1, RX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_L5, NONE, RSMRST, NF1),
|
||||||
/* GPP_L6 - TESTCH0_D4 */
|
/* GPP_L6 - TESTCH0_D4 */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_L6, NONE, RSMRST, NF1, RX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_L6, NONE, RSMRST, NF1),
|
||||||
/* GPP_L7 - TESTCH0_D5 */
|
/* GPP_L7 - TESTCH0_D5 */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_L7, NONE, RSMRST, NF1, RX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_L7, NONE, RSMRST, NF1),
|
||||||
/* GPP_L8 - TESTCH0_D6 */
|
/* GPP_L8 - TESTCH0_D6 */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_L8, NONE, RSMRST, NF1, RX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_L8, NONE, RSMRST, NF1),
|
||||||
/* GPP_L9 - TESTCH0_D7 */
|
/* GPP_L9 - TESTCH0_D7 */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_L9, NONE, RSMRST, NF1, RX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_L9, NONE, RSMRST, NF1),
|
||||||
/* GPP_L10 - TESTCH0_CLK */
|
/* GPP_L10 - TESTCH0_CLK */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_L10, NONE, RSMRST, NF1, RX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_L10, NONE, RSMRST, NF1),
|
||||||
/* GPP_L11 - TESTCH1_D0 */
|
/* GPP_L11 - TESTCH1_D0 */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_L11, NONE, RSMRST, NF1, RX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_L11, NONE, RSMRST, NF1),
|
||||||
/* GPP_L12 - TESTCH1_D1 */
|
/* GPP_L12 - TESTCH1_D1 */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_L12, NONE, RSMRST, NF1, RX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_L12, NONE, RSMRST, NF1),
|
||||||
/* GPP_L13 - TESTCH1_D2 */
|
/* GPP_L13 - TESTCH1_D2 */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_L13, NONE, RSMRST, NF1, RX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_L13, NONE, RSMRST, NF1),
|
||||||
/* GPP_L14 - TESTCH1_D3 */
|
/* GPP_L14 - TESTCH1_D3 */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_L14, NONE, RSMRST, NF1, RX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_L14, NONE, RSMRST, NF1),
|
||||||
/* GPP_L15 - TESTCH1_D4 */
|
/* GPP_L15 - TESTCH1_D4 */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_L15, NONE, RSMRST, NF1, RX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_L15, NONE, RSMRST, NF1),
|
||||||
/* GPP_L16 - TESTCH1_D5 */
|
/* GPP_L16 - TESTCH1_D5 */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_L16, NONE, RSMRST, NF1, RX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_L16, NONE, RSMRST, NF1),
|
||||||
/* GPP_L17 - TESTCH1_D6 */
|
/* GPP_L17 - TESTCH1_D6 */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_L17, NONE, RSMRST, NF1, RX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_L17, NONE, RSMRST, NF1),
|
||||||
/* GPP_L18 - TESTCH1_D7 */
|
/* GPP_L18 - TESTCH1_D7 */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_L18, NONE, RSMRST, NF1, RX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_L18, NONE, RSMRST, NF1),
|
||||||
/* GPP_L19 - TESTCH1_CLK */
|
/* GPP_L19 - TESTCH1_CLK */
|
||||||
PAD_CFG_NF_BUF_TRIG(GPP_L19, NONE, RSMRST, NF1, RX_DISABLE, OFF),
|
PAD_CFG_NF(GPP_L19, NONE, RSMRST, NF1),
|
||||||
};
|
};
|
||||||
|
|
||||||
#endif /* CFG_PCH_GPIO_H */
|
#endif /* CFG_PCH_GPIO_H */
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue