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mb/asus/p5qpl-am: Add p5g41t-m_lx as a variant 

This board has more or less the same as the p5qpl-am except for DDR3
memory and different colors on the ports. Tested with Arch Linux with
kernel 4.20.0-arch1-1-ARCH.

What is tested and works:
 - 800/1066/1333 MHz CPUs and DDR3 sticks at 800/1066 MHz
     Some bugs are still present in the DDR3 raminit code though.
 - Ethernet
 - Internal programmer with both coreboot and stock firmware.
 - PCI and PCIe x1 slots
 - All USB ports
 - S3 resume
 - SATA ports
 - PEG
 - Rear audio output

Change-Id: I92cd15a245c4f1d8f57b304c9c3a37ba29c35431
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/27089
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2018-06-13 14:13:15 +02:00 committed by Patrick Georgi
parent e124fa5a9d
commit c69c8ddc2b
9 changed files with 395 additions and 91 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
src/mainboard/asus/p5qpl-am/Kconfig
View File

@ -14,7 +14,7 @@
# GNU General Public License for more details.
#
if BOARD_ASUS_P5QPL_AM
if BOARD_ASUS_P5QPL_AM || BOARD_ASUS_P5G41T_M_LX
config BOARD_SPECIFIC_OPTIONS
def_bool y
@ -33,18 +33,34 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_ACPI_RESUME
select INTEL_GMA_HAVE_VBT
select MAINBOARD_HAS_LIBGFXINIT
select ATHEROS_ATL1E_SETMAC
# P5G41T-M LX has ATL1C which works fine
select ATHEROS_ATL1E_SETMAC if BOARD_ASUS_P5QPL_AM
config MAINBOARD_DIR
string
default "asus/p5qpl-am"
config VARIANT_DIR
string
default "p5qpl-am" if BOARD_ASUS_P5QPL_AM
default "p5g41t-m_lx" if BOARD_ASUS_P5G41T_M_LX
config MAINBOARD_PART_NUMBER
string
default "P5QPL-AM"
default "P5QPL-AM" if BOARD_ASUS_P5QPL_AM
default "P5G41T-M LX" if BOARD_ASUS_P5G41T_M_LX
config OVERRIDE_DEVICETREE
string
default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
config MAX_CPUS
int
default 4
endif # BOARD_ASUS_P5QPL_AM
# Override the default variant behavior, since the data.vbt is the same
config INTEL_GMA_VBT_FILE
default "src/mainboard/$(MAINBOARDDIR)/data.vbt"
endif # BOARD_ASUS_P5QPL_AM || BOARD_ASUS_P5G41T_M_LX

3
src/mainboard/asus/p5qpl-am/Kconfig.name
View File

@ -1,2 +1,5 @@
config BOARD_ASUS_P5QPL_AM
bool "P5QPL-AM"
config BOARD_ASUS_P5G41T_M_LX
bool "P5G41T-M LX"

2
src/mainboard/asus/p5qpl-am/Makefile.inc
View File

@ -1,4 +1,4 @@
ramstage-y += cstates.c
romstage-y += gpio.c
romstage-y += variants/$(VARIANT_DIR)/gpio.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

76
src/mainboard/asus/p5qpl-am/devicetree.cb
View File

@ -2,6 +2,7 @@
# This file is part of the coreboot project.
#
# Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
# Copyright (C) 2019 Angel Pons <th3fanbus@gmail.com>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
@ -24,7 +25,6 @@ chip northbridge/intel/x4x # Northbridge
end
end
device domain 0 on # PCI domain
subsystemid 0x1043 0x836d inherit
device pci 0.0 on end # Host Bridge
device pci 1.0 on end # PEG
device pci 2.0 on end # Integrated graphics controller
@ -46,76 +46,26 @@ chip northbridge/intel/x4x # Northbridge
register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant
register "gpe0_en" = "0x04000440"
device pci 1b.0 on end # Audio
device pci 1c.0 on end # PCIe 1
device pci 1b.0 on end # Audio
device pci 1c.0 on end # PCIe 1: PCIe x1 slot
device pci 1c.1 on # PCIe 2: NIC
device pci 00.0 on
end
end
device pci 1c.2 off end # PCIe 3
device pci 1c.3 off end # PCIe 4
device pci 1c.4 off end # PCIe 5
device pci 1c.5 off end # PCIe 6
device pci 1d.0 on end # USB
device pci 1d.1 on end # USB
device pci 1d.2 on end # USB
device pci 1d.3 on end # USB
device pci 1d.7 on end # USB
device pci 1e.0 on end # PCI bridge
device pci 1d.0 on end # USB
device pci 1d.1 on end # USB
device pci 1d.2 on end # USB
device pci 1d.3 on end # USB
device pci 1d.7 on end # USB
device pci 1e.0 on end # PCI bridge
device pci 1e.2 off end # AC'97 Audio Controller
device pci 1e.3 off end # AC'97 Modem Controller
device pci 1f.0 on # ISA bridge
chip superio/winbond/w83627dhg
device pnp 2e.0 off end # Floppy
device pnp 2e.1 on # Parallel port
# global
irq 0x2c = 0x92
# parallel port
io 0x60 = 0x378
irq 0x70 = 7
drq 0x74 = 3
end
device pnp 2e.2 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 off end # COM2, IR
device pnp 2e.5 on # Keyboard, mouse
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 2e.6 off end # SPI
device pnp 2e.7 on end # GPIO6 (all input)
device pnp 2e.8 off end # WDT0#, PLED
device pnp 2e.9 off end # GPIO2
device pnp 2e.109 on # GPIO3
irq 0xf0 = 0xf3
# irq 0xf1 = 0x08
end
device pnp 2e.209 on # GPIO4
irq 0xf4 = 0x00
end
device pnp 2e.309 off end # GPIO5
device pnp 2e.a on # ACPI
irq 0x70 = 0
irq 0xe4 = 0x10 # VSBGATE# to power dram during S3
end
device pnp 2e.b on # HWM, front pannel LED
io 0x60 = 0x290
irq 0x70 = 0
end
device pnp 2e.c on # PECI, SST
irq 0xe0 = 0x10
irq 0xe1 = 0x64
irq 0xe8 = 0x01
end
end
end
device pci 1f.1 on end # PATA/IDE
device pci 1f.2 on end # SATA
device pci 1f.3 on end # SMbus
device pci 1f.0 on end # ISA bridge
device pci 1f.1 on end # PATA/IDE
device pci 1f.2 on end # SATA
device pci 1f.3 on end # SMbus
end
end
end

69
src/mainboard/asus/p5qpl-am/romstage.c
View File

@ -51,12 +51,7 @@ static u8 msr_get_fsb(void)
return fsbcfg;
}
/*
* BSEL MCH straps are not hooked up to the CPU as usual but to the SIO
* BSEL0 -> not hooked up (such configs are not supported anyways)
* BSEL1 -> GPIO33
* BSEL2 -> GPIO40
*/
/* BSEL MCH straps are not hooked up to the CPU as usual but to the SIO */
static int setup_sio_gpio(void)
{
@ -79,27 +74,55 @@ static int setup_sio_gpio(void)
pnp_enter_ext_func_mode(GPIO_DEV);
pnp_set_logical_device(GPIO_DEV);
reg = 0x92;
old_reg = pnp_read_config(GPIO_DEV, 0x2c);
pnp_write_config(GPIO_DEV, 0x2c, reg);
need_reset = (reg != old_reg);
if (IS_ENABLED(CONFIG_BOARD_ASUS_P5QPL_AM)) {
/*
* P5QPL-AM:
* BSEL0 -> not hooked up (not supported anyways)
* BSEL1 -> GPIO33
* BSEL2 -> GPIO40
*/
reg = 0x92;
old_reg = pnp_read_config(GPIO_DEV, 0x2c);
pnp_write_config(GPIO_DEV, 0x2c, reg);
need_reset = (reg != old_reg);
pnp_write_config(GPIO_DEV, 0x30, 0x06);
pnp_write_config(GPIO_DEV, 0xf0, 0xf3); /* GPIO3 direction */
pnp_write_config(GPIO_DEV, 0xf4, 0x00); /* GPIO4 direction */
pnp_write_config(GPIO_DEV, 0x30, 0x06);
pnp_write_config(GPIO_DEV, 0xf0, 0xf3); /* GPIO3 direction */
pnp_write_config(GPIO_DEV, 0xf4, 0x00); /* GPIO4 direction */
int gpio33 = (bsel & 2) >> 1;
int gpio40 = (bsel & 4) >> 2;
reg = (gpio33 << 3);
old_reg = pnp_read_config(GPIO_DEV, 0xf1);
pnp_write_config(GPIO_DEV, 0xf1, old_reg | reg);
need_reset += ((reg & 0x8) != (old_reg & 0x8));
const int gpio33 = (bsel & 2) >> 1;
const int gpio40 = (bsel & 4) >> 2;
reg = (gpio33 << 3);
old_reg = pnp_read_config(GPIO_DEV, 0xf1);
pnp_write_config(GPIO_DEV, 0xf1, old_reg | reg);
need_reset += ((reg & 0x8) != (old_reg & 0x8));
reg = gpio40;
old_reg = pnp_read_config(GPIO_DEV, 0xf5);
pnp_write_config(GPIO_DEV, 0xf5, old_reg | reg);
need_reset += ((reg & 0x1) != (old_reg & 0x1));
reg = gpio40;
old_reg = pnp_read_config(GPIO_DEV, 0xf5);
pnp_write_config(GPIO_DEV, 0xf5, old_reg | reg);
need_reset += ((reg & 0x1) != (old_reg & 0x1));
} else {
/*
* P5G41T-M LX:
* BSEL0 -> not hooked up
* BSEL1 -> GPIO43 (inverted)
* BSEL2 -> GPIO44
*/
reg = 0xf2;
old_reg = pnp_read_config(GPIO_DEV, 0x2c);
pnp_write_config(GPIO_DEV, 0x2c, reg);
need_reset = (reg != old_reg);
pnp_write_config(GPIO_DEV, 0x30, 0x05);
pnp_write_config(GPIO_DEV, 0xf6, 0x08); /* invert GPIO43 */
pnp_write_config(GPIO_DEV, 0xf4, 0x00); /* GPIO4 direction */
const int gpio43 = (bsel & 2) >> 1;
const int gpio44 = (bsel & 4) >> 2;
reg = (gpio43 << 3) | (gpio44 << 4);
old_reg = pnp_read_config(GPIO_DEV, 0xf5);
pnp_write_config(GPIO_DEV, 0xf5, old_reg | reg);
need_reset += ((reg & 0x18) != (old_reg & 0x18));
}
pnp_exit_ext_func_mode(GPIO_DEV);
return need_reset;

161
src/mainboard/asus/p5qpl-am/variants/p5g41t-m_lx/gpio.c Normal file
View File

@ -0,0 +1,161 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2018 Angel Pons <th3fanbus@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <southbridge/intel/common/gpio.h>
const struct pch_gpio_set1 pch_gpio_set1_mode = {
.gpio0 = GPIO_MODE_GPIO,
.gpio1 = GPIO_MODE_NATIVE,
.gpio2 = GPIO_MODE_NATIVE,
.gpio3 = GPIO_MODE_NATIVE,
.gpio4 = GPIO_MODE_NATIVE,
.gpio5 = GPIO_MODE_NATIVE,
.gpio6 = GPIO_MODE_GPIO,
.gpio7 = GPIO_MODE_GPIO,
.gpio8 = GPIO_MODE_GPIO,
.gpio9 = GPIO_MODE_GPIO,
.gpio10 = GPIO_MODE_GPIO,
.gpio11 = GPIO_MODE_NATIVE,
.gpio12 = GPIO_MODE_GPIO,
.gpio13 = GPIO_MODE_GPIO,
.gpio14 = GPIO_MODE_GPIO,
.gpio15 = GPIO_MODE_GPIO,
.gpio16 = GPIO_MODE_GPIO,
.gpio17 = GPIO_MODE_NATIVE,
.gpio18 = GPIO_MODE_GPIO,
.gpio19 = GPIO_MODE_GPIO,
.gpio20 = GPIO_MODE_GPIO,
.gpio21 = GPIO_MODE_GPIO,
.gpio22 = GPIO_MODE_NATIVE,
.gpio23 = GPIO_MODE_NATIVE,
.gpio24 = GPIO_MODE_GPIO,
.gpio25 = GPIO_MODE_GPIO,
.gpio26 = GPIO_MODE_GPIO,
.gpio27 = GPIO_MODE_GPIO,
.gpio28 = GPIO_MODE_GPIO,
.gpio29 = GPIO_MODE_NATIVE,
.gpio30 = GPIO_MODE_NATIVE,
.gpio31 = GPIO_MODE_NATIVE,
};
const struct pch_gpio_set1 pch_gpio_set1_direction = {
.gpio0 = GPIO_DIR_INPUT,
.gpio1 = GPIO_DIR_INPUT,
.gpio2 = GPIO_DIR_OUTPUT,
.gpio3 = GPIO_DIR_OUTPUT,
.gpio4 = GPIO_DIR_OUTPUT,
.gpio5 = GPIO_DIR_OUTPUT,
.gpio6 = GPIO_DIR_INPUT,
.gpio7 = GPIO_DIR_INPUT,
.gpio8 = GPIO_DIR_OUTPUT,
.gpio9 = GPIO_DIR_INPUT,
.gpio10 = GPIO_DIR_INPUT,
.gpio11 = GPIO_DIR_INPUT,
.gpio12 = GPIO_DIR_OUTPUT,
.gpio13 = GPIO_DIR_INPUT,
.gpio14 = GPIO_DIR_INPUT,
.gpio15 = GPIO_DIR_OUTPUT,
.gpio16 = GPIO_DIR_OUTPUT,
.gpio17 = GPIO_DIR_OUTPUT,
.gpio18 = GPIO_DIR_OUTPUT,
.gpio19 = GPIO_DIR_INPUT,
.gpio20 = GPIO_DIR_OUTPUT,
.gpio21 = GPIO_DIR_OUTPUT,
.gpio22 = GPIO_DIR_INPUT,
.gpio23 = GPIO_DIR_INPUT,
.gpio24 = GPIO_DIR_OUTPUT,
.gpio25 = GPIO_DIR_OUTPUT,
.gpio26 = GPIO_DIR_OUTPUT,
.gpio27 = GPIO_DIR_OUTPUT,
.gpio28 = GPIO_DIR_OUTPUT,
.gpio29 = GPIO_DIR_INPUT,
.gpio30 = GPIO_DIR_INPUT,
.gpio31 = GPIO_DIR_INPUT,
};
const struct pch_gpio_set1 pch_gpio_set1_level = {
.gpio0 = GPIO_LEVEL_HIGH,
.gpio6 = GPIO_LEVEL_HIGH,
.gpio7 = GPIO_LEVEL_LOW,
.gpio8 = GPIO_LEVEL_LOW,
.gpio9 = GPIO_LEVEL_HIGH,
.gpio10 = GPIO_LEVEL_HIGH,
.gpio12 = GPIO_LEVEL_HIGH,
.gpio13 = GPIO_LEVEL_HIGH,
.gpio14 = GPIO_LEVEL_LOW,
.gpio15 = GPIO_LEVEL_HIGH,
.gpio16 = GPIO_LEVEL_LOW,
.gpio18 = GPIO_LEVEL_HIGH,
.gpio19 = GPIO_LEVEL_HIGH,
.gpio20 = GPIO_LEVEL_LOW,
.gpio21 = GPIO_LEVEL_HIGH,
.gpio24 = GPIO_LEVEL_LOW,
.gpio25 = GPIO_LEVEL_HIGH,
.gpio26 = GPIO_LEVEL_LOW,
.gpio27 = GPIO_LEVEL_LOW,
.gpio28 = GPIO_LEVEL_LOW,
};
const struct pch_gpio_set1 pch_gpio_set1_invert = {
.gpio10 = GPIO_INVERT,
.gpio13 = GPIO_INVERT,
};
const struct pch_gpio_set2 pch_gpio_set2_mode = {
.gpio32 = GPIO_MODE_GPIO,
.gpio33 = GPIO_MODE_GPIO,
.gpio34 = GPIO_MODE_GPIO,
.gpio35 = GPIO_MODE_GPIO,
.gpio36 = GPIO_MODE_GPIO,
.gpio37 = GPIO_MODE_GPIO,
.gpio38 = GPIO_MODE_GPIO,
.gpio39 = GPIO_MODE_GPIO,
};
const struct pch_gpio_set2 pch_gpio_set2_direction = {
.gpio32 = GPIO_DIR_OUTPUT,
.gpio33 = GPIO_DIR_OUTPUT,
.gpio34 = GPIO_DIR_OUTPUT,
.gpio35 = GPIO_DIR_OUTPUT,
.gpio36 = GPIO_DIR_INPUT,
.gpio37 = GPIO_DIR_INPUT,
.gpio38 = GPIO_DIR_INPUT,
.gpio39 = GPIO_DIR_INPUT,
};
const struct pch_gpio_set2 pch_gpio_set2_level = {
.gpio32 = GPIO_LEVEL_HIGH,
.gpio33 = GPIO_LEVEL_HIGH,
.gpio34 = GPIO_LEVEL_LOW,
.gpio35 = GPIO_LEVEL_LOW,
.gpio36 = GPIO_LEVEL_HIGH,
.gpio37 = GPIO_LEVEL_HIGH,
.gpio38 = GPIO_LEVEL_HIGH,
.gpio39 = GPIO_LEVEL_HIGH,
};
const struct pch_gpio_map mainboard_gpio_map = {
.set1 = {
.mode = &pch_gpio_set1_mode,
.direction = &pch_gpio_set1_direction,
.level = &pch_gpio_set1_level,
.invert = &pch_gpio_set1_invert,
},
.set2 = {
.mode = &pch_gpio_set2_mode,
.direction = &pch_gpio_set2_direction,
.level = &pch_gpio_set2_level,
},
};

80
src/mainboard/asus/p5qpl-am/variants/p5g41t-m_lx/overridetree.cb Normal file
View File

@ -0,0 +1,80 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
# Copyright (C) 2019 Angel Pons <th3fanbus@gmail.com>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
chip northbridge/intel/x4x # Northbridge
device domain 0 on # PCI domain
subsystemid 0x1043 0x8179 inherit
chip southbridge/intel/i82801gx # Southbridge
device pci 1f.0 on # ISA bridge
chip superio/winbond/w83627dhg
device pnp 2e.0 off end # Floppy
device pnp 2e.1 on # Parallel port
# global
irq 0x2c = 0xf2
# parallel port
io 0x60 = 0x378
irq 0x70 = 7
drq 0x74 = 3
end
device pnp 2e.2 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 off end # COM2, IR
device pnp 2e.5 on # Keyboard, mouse
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 2e.6 off end # SPI
device pnp 2e.7 on end # GPIO6 (all input)
device pnp 2e.8 off end # WDT0#, PLED
device pnp 2e.9 on # GPIO2
irq 0xe4 = 0x04
end
device pnp 2e.109 off end # GPIO3
device pnp 2e.209 on # GPIO4
irq 0xe8 = 0x80
irq 0xf4 = 0xa4
irq 0xf5 = 0x46
end
device pnp 2e.309 on # GPIO5
irq 0xfa = 0xff
irq 0xf3 = 0x09 # RSVD SUSLED settings
end
device pnp 2e.a on # ACPI
irq 0xe4 = 0x10 # Power dram during s3
irq 0xe6 = 0x8c
irq 0xf2 = 0x7d
end
device pnp 2e.b on # HWM, front panel LED
io 0x60 = 0x290
irq 0x70 = 0
irq 0xf1 = 0xff
irq 0xf2 = 0x83
end
device pnp 2e.c on # PECI, SST
irq 0xe0 = 0x10
irq 0xe1 = 0x64
irq 0xe8 = 0x01
end
end
end
end
end
end

0
src/mainboard/asus/p5qpl-am/gpio.c → src/mainboard/asus/p5qpl-am/variants/p5qpl-am/gpio.c
View File

71
src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb Normal file
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@ -0,0 +1,71 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
chip northbridge/intel/x4x # Northbridge
device domain 0 on # PCI domain
subsystemid 0x1043 0x836d inherit
chip southbridge/intel/i82801gx # Southbridge
device pci 1f.0 on # ISA bridge
chip superio/winbond/w83627dhg
device pnp 2e.0 off end # Floppy
device pnp 2e.1 on # Parallel port
# global
irq 0x2c = 0x92
# parallel port
io 0x60 = 0x378
irq 0x70 = 7
drq 0x74 = 3
end
device pnp 2e.2 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 off end # COM2, IR
device pnp 2e.5 on # Keyboard, mouse
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 2e.6 off end # SPI
device pnp 2e.7 on end # GPIO6 (all input)
device pnp 2e.8 off end # WDT0#, PLED
device pnp 2e.9 off end # GPIO2
device pnp 2e.109 on # GPIO3
irq 0xf0 = 0xf3
end
device pnp 2e.209 on # GPIO4
irq 0xf4 = 0x00
end
device pnp 2e.309 off end # GPIO5
device pnp 2e.a on # ACPI
irq 0x70 = 0
irq 0xe4 = 0x10 # VSBGATE# to power dram during S3
end
device pnp 2e.b on # HWM, front pannel LED
io 0x60 = 0x290
irq 0x70 = 0
end
device pnp 2e.c on # PECI, SST
irq 0xe0 = 0x10
irq 0xe1 = 0x64
irq 0xe8 = 0x01
end
end
end
end
end
end