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soc/amd/cezanne/fw.cfg: provide default SPL table binary 

Chause doesn't get to x86 bootblock without the SPL table binary in the
PSP directory table, so I assume that Majolica won't get to x86
bootblock either, since the Cezanne SoC default is not to include any
SPL table binary. This was caused by a combination of
commit 6c5ec8e31c (amdfwtool: Add options
to support mainboard specific SPL table) that caused a regression in
amdfwtool and commit c5b912f788
(soc/amd/cezanne: Allow to specify SPL table path in Kconfig) that
removed the default for the Cezanne SoC. Fix this by adding the default
SPL table file back to the fw.cfg file which will get ignored by
amdfwtool when a mainboard selects SPL_TABLE_FILE and specifies another
SPL table binary.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ica960e5422da50899a2d9c192863188174e0bcff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Felix Held 2022-04-02 04:06:12 +02:00
parent 11b0d360ba
commit c6b71bc614
1 changed files with 1 additions and 0 deletions
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src/soc/amd/cezanne/fw.cfg
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@ -29,6 +29,7 @@ UNIFIEDUSB_FILE TypeId0x44_UnifiedUsb_CZN.sbin
DRTMTA_FILE TypeId0x47_DrtmTA_CZN.sbin DRTMTA_FILE TypeId0x47_DrtmTA_CZN.sbin
KEYDBBL_FILE TypeId0x50_KeyDbBl_CZN.sbin KEYDBBL_FILE TypeId0x50_KeyDbBl_CZN.sbin
KEYDB_TOS_FILE TypeId0x51_KeyDbTos_CZN.sbin KEYDB_TOS_FILE TypeId0x51_KeyDbTos_CZN.sbin
SPL_TABLE_FILE TypeId0x55_SplTableBl_CZN.sbin
DMCUERAMDCN21_FILE TypeId0x58_DmcuEramDcn21.sbin DMCUERAMDCN21_FILE TypeId0x58_DmcuEramDcn21.sbin
DMCUINTVECTORSDCN21_FILE TypeId0x59_DmcuIntvectorsDcn21.sbin DMCUINTVECTORSDCN21_FILE TypeId0x59_DmcuIntvectorsDcn21.sbin
PSPBTLDR_AB_FILE TypeId0x73_PspBootLoader_AB_CZN.sbin PSPBTLDR_AB_FILE TypeId0x73_PspBootLoader_AB_CZN.sbin