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yhlu's pnp patch 

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1518 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Li-Ta Lo 2004-04-21 16:57:05 +00:00
parent 771b1aefa3
commit c6bcedb2c4
5 changed files with 153 additions and 39 deletions
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19
src/devices/pnp_device.c
View File

@ -118,6 +118,7 @@ void pnp_set_resources(device_t dev)
for(i = 0; i < dev->resources; i++) {
pnp_set_resource(dev, &dev->resource[i]);
}
}
void pnp_enable_resources(device_t dev)
@ -129,8 +130,9 @@ void pnp_enable_resources(device_t dev)
void pnp_enable(device_t dev)
{
pnp_set_logical_device(dev);
if (!dev->enable) {
if (!dev->enable) {
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
}
}
@ -165,7 +167,7 @@ static void get_resources(device_t dev, struct pnp_info *info)
{
struct resource *resource;
pnp_set_logical_device(dev);
// pnp_set_logical_device(dev); // coment out by LYH
if (info->flags & PNP_IO0) {
pnp_get_ioresource(dev, PNP_IDX_IO0, &info->io0);
@ -207,11 +209,20 @@ void pnp_enumerate(struct chip *chip, unsigned functions,
path.type = DEVICE_PATH_PNP;
path.u.pnp.port = chip->dev->path.u.pnp.port;
/* Setup the ops and resources on the newly allocated devices */
for(i = 0; i < functions; i++) {
path.u.pnp.device = info[i].function;
dev = alloc_find_dev(chip->bus, &path);
dev->ops = ops;
if(info[i].ops == 0) { // BY LYH
dev->ops = ops;
}
else {
dev->ops = info[i].ops; // BY LYH
}
get_resources(dev, &info[i]);
}
}

9
src/mainboard/tyan/s2882/Config.lb
View File

@ -132,7 +132,8 @@ end
makerule ./failover.inc
depends "./romcc ./failover.E"
action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"end
action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c option_table.h"
@ -149,6 +150,7 @@ mainboardinit cpu/k8/disable_mmx_sse.inc
###
### Include the secondary Configuration files
###
northbridge amd/amdk8 "mc0"
pci 0:18.0
pci 0:18.0
@ -175,7 +177,7 @@ northbridge amd/amdk8 "mc0"
pci 1:0.2 on
pci 1:1.0 off
superio winbond/w83627hf link 1
pnp 2e.0 off # Floppy
pnp 2e.0 on # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
@ -198,7 +200,8 @@ northbridge amd/amdk8 "mc0"
pnp 2e.8 off # GPIO2
pnp 2e.9 off # GPIO3
pnp 2e.a off # ACPI
pnp 2e.b off # HW Monitor
pnp 2e.b on # HW Monitor
io 0x60 = 0x290
end
end
end

10
src/mainboard/tyan/s2885/Config.lb
View File

@ -36,9 +36,9 @@ default LB_CKS_LOC=123
driver mainboard.o
#driver broadcom_nic.o
#driver ti_firewire.o
driver ti_firewire.o
#driver adaptec_scsi.o
#driver si_sata.o
driver si_sata.o
#driver intel_nic.o
#object reset.o
if HAVE_MP_TABLE object mptable.o end
@ -176,7 +176,7 @@ northbridge amd/amdk8 "mc0"
pci 1:0.2 on
pci 1:1.0 off
superio winbond/w83627hf link 1
pnp 2e.0 off # Floppy
pnp 2e.0 on # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
@ -199,7 +199,8 @@ northbridge amd/amdk8 "mc0"
pnp 2e.8 off # GPIO2
pnp 2e.9 off # GPIO3
pnp 2e.a off # ACPI
pnp 2e.b off # HW Monitor
pnp 2e.b on # HW Monitor
io 0x60 = 0x290
end
end
southbridge amd/amd8151 "amd8151" link 0
@ -217,7 +218,6 @@ northbridge amd/amdk8 "mc1"
pci 0:19.3
end
dir /pc80
#dir /bioscall
cpu k8 "cpu0"

142
src/superio/winbond/w83627hf/superio.c
View File

@ -16,13 +16,73 @@
#include "chip.h"
#include "w83627hf.h"
static void init(device_t dev)
//BY LYH
void pnp_enter_ext_func_mode(device_t dev) {
outb(0x87, dev->path.u.pnp.port);
outb(0x87, dev->path.u.pnp.port);
}
void pnp_exit_ext_func_mode(device_t dev) {
outb(0xaa, dev->path.u.pnp.port);
}
void pnp_write_hwm(unsigned long port_base, uint8_t reg, uint8_t value)
{
outb(reg, port_base+5);
outb(value, port_base+6);
}
uint8_t pnp_read_hwm(unsigned long port_base, uint8_t reg)
{
outb(reg, port_base + 5);
return inb(port_base + 6);
}
static void enable_hwm_smbus(device_t dev) {
uint8_t reg, value;
reg = 0x2b;
value = pnp_read_config(dev, reg);
value &= 0x3f;
pnp_write_config(dev, reg, value);
}
static void init_hwm(unsigned long base)
{
uint8_t reg, value;
int i;
unsigned hwm_reg_values[] = {
// reg mask data
0x40 , 0xff , 0x81, // ; Start Hardware Monitoring for WIN627
0x48 , 0xC8 , 0x48, // ; Program SIO SMBus BAR to 90h>>1
0x4A , 0x21 , 0x21, // ; Program T2 SMBus BAR to 92h>>1 &
// ; Program T3 SMBus BAR to 94h>>1
0x4E , 0x80 , 0x00,
0x43 , 0x00 , 0xFF,
0x44 , 0x00 , 0x3F,
0x4C , 0xBF , 0x18,
0x4D , 0xFF , 0x80 // ; Turn Off Beep
};
for(i = 0; i< sizeof(hwm_reg_values)/sizeof(hwm_reg_values[0]); i+=3 ) {
reg = hwm_reg_values[i];
value = pnp_read_hwm(base, reg);
value &= 0xff & hwm_reg_values[i+1];
value |= 0xff & hwm_reg_values[i+2];
#if 0
printk_debug("base = 0x%04x, reg = 0x%02x, value = 0x%02x\r\n", base,reg,value);
#endif
pnp_write_hwm(base,reg, value);
}
}
//END
static void w83627hf_init(device_t dev)
{
struct superio_winbond_w83627hf_config *conf;
struct resource *res0, *res1;
/* Wishlist handle well known programming interfaces more
* generically.
*/
if (!dev->enable) {
return;
}
@ -41,15 +101,61 @@ static void init(device_t dev)
res1 = get_resource(dev, PNP_IDX_IO1);
init_pc_keyboard(res0->base, res1->base, &conf->keyboard);
break;
//BY LYH
case W83627HF_HWM:
res0 = get_resource(dev, PNP_IDX_IO0);
init_hwm(res0->base);
break;
//END
}
}
void w83627hf_pnp_set_resources(device_t dev)
{
pnp_enter_ext_func_mode(dev); //BY LYH
pnp_set_resources(dev);
pnp_exit_ext_func_mode(dev); //BY LYH
}
void w83627hf_pnp_enable_resources(device_t dev)
{
pnp_enter_ext_func_mode(dev); //BY LYH
pnp_enable_resources(dev);
if(dev->path.u.pnp.device == W83627HF_HWM) {
//set the pin 91,92 as I2C bus
printk_debug("w83627hf hwm smbus enabled\r\n");
enable_hwm_smbus(dev);
}
pnp_exit_ext_func_mode(dev); //BY LYH
}
void w83627hf_pnp_enable(device_t dev)
{
if (!dev->enable) {
pnp_enter_ext_func_mode(dev); // BY LYH
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_exit_ext_func_mode(dev); //BY LYH
}
}
static struct device_operations ops = {
.read_resources = pnp_read_resources,
.set_resources = pnp_set_resources,
.enable_resources = pnp_enable_resources,
.enable = pnp_enable,
.init = init,
.set_resources = w83627hf_pnp_set_resources,
.enable_resources = w83627hf_pnp_enable_resources,
.enable = w83627hf_pnp_enable,
.init = w83627hf_init,
};
static struct pnp_info pnp_dev_info[] = {
@ -61,8 +167,8 @@ static struct pnp_info pnp_dev_info[] = {
{ &ops, W83627HF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
{ &ops, W83627HF_CIR, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, W83627HF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 4} },
// { W83627HF_GPIO2,},
// { W83627HF_GPIO3,},
{ &ops, W83627HF_GPIO2,},
{ &ops, W83627HF_GPIO3,},
{ &ops, W83627HF_ACPI, PNP_IRQ0, },
{ &ops, W83627HF_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 } },
};
@ -72,24 +178,8 @@ static void enumerate(struct chip *chip)
pnp_enumerate(chip, sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]),
&pnp_ops, pnp_dev_info);
}
static void sio_enable(struct chip *chip, enum chip_pass pass)
{
struct superio_winbond_w83627hf_config *conf = (struct superio_winbond_w83627hf_config *)chip->chip_info;
switch (pass) {
case CONF_PASS_PRE_CONSOLE:
init_pc_keyboard(0x60, 0x64, &conf->keyboard);
break;
default:
/* nothing yet */
break;
}
}
struct chip_control superio_winbond_w83627hf_control = {
.enable = sio_enable,
.enumerate = enumerate,
.name = "Winbond w83627hf"
};

12
src/superio/winbond/w83627hf/w83627hf_early_serial.c
View File

@ -1,11 +1,21 @@
#include <arch/romcc_io.h>
#include "w83627hf.h"
static inline void pnp_enter_ext_func_mode(device_t dev) {
unsigned port = dev>>8;
outb(0x87, port);
outb(0x87, port);
}
static void pnp_exit_ext_func_mode(device_t dev) {
unsigned port = dev>>8;
outb(0xaa, port);
}
static void w83627hf_enable_serial(device_t dev, unsigned iobase)
{
pnp_enter_ext_func_mode(dev);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
pnp_set_enable(dev, 1);
pnp_exit_ext_func_mode(dev);
}