amd/stoneyridge: Clean up smihandler.c
Replace hardcoded values with defined ones. Change-Id: Ic72a51516a1763b2380e60397f5a3aeb32457b65 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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@ -11,18 +11,6 @@
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#include <soc/smi.h>
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#include <soc/smi.h>
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#include <soc/southbridge.h>
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#include <soc/southbridge.h>
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#define SMI_0x88_ACPI_COMMAND (1 << 11)
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enum smi_source {
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SMI_SOURCE_SCI = (1 << 0),
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SMI_SOURCE_GPE = (1 << 1),
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SMI_SOURCE_0x84 = (1 << 2),
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SMI_SOURCE_0x88 = (1 << 3),
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SMI_SOURCE_IRQ_TRAP = (1 << 4),
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SMI_SOURCE_0x90 = (1 << 5)
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};
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static void sb_apmc_smi_handler(void)
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static void sb_apmc_smi_handler(void)
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{
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{
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u32 reg32;
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u32 reg32;
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@ -51,78 +39,77 @@ int southbridge_io_trap_handler(int smif)
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static void process_smi_sci(void)
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static void process_smi_sci(void)
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{
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{
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const uint32_t status = smi_read32(0x10);
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const uint32_t status = smi_read32(SMI_SCI_STATUS);
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/* Clear events to prevent re-entering SMI if event isn't handled */
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/* Clear events to prevent re-entering SMI if event isn't handled */
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smi_write32(0x10, status);
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smi_write32(SMI_SCI_STATUS, status);
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}
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}
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static void process_gpe_smi(void)
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static void process_gpe_smi(void)
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{
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{
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const uint32_t status = smi_read32(0x80);
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const uint32_t status = smi_read32(SMI_REG_SMISTS0);
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const uint32_t gevent_mask = (1 << 24) - 1;
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/* Only Bits [23:0] indicate GEVENT SMIs. */
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/* Only Bits [23:0] indicate GEVENT SMIs. */
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if (status & gevent_mask) {
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if (status & GEVENT_MASK) {
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/* A GEVENT SMI occurred */
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/* A GEVENT SMI occurred */
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mainboard_smi_gpi(status & gevent_mask);
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mainboard_smi_gpi(status & GEVENT_MASK);
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}
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}
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/* Clear events to prevent re-entering SMI if event isn't handled */
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/* Clear events to prevent re-entering SMI if event isn't handled */
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smi_write32(0x80, status);
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smi_write32(SMI_REG_SMISTS0, status);
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}
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}
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static void process_smi_0x84(void)
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static void process_smi_0x84(void)
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{
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{
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const uint32_t status = smi_read32(0x84);
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const uint32_t status = smi_read32(SMI_REG_SMISTS1);
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/* Clear events to prevent re-entering SMI if event isn't handled */
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/* Clear events to prevent re-entering SMI if event isn't handled */
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smi_write32(0x84, status);
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smi_write32(SMI_REG_SMISTS1, status);
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}
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}
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static void process_smi_0x88(void)
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static void process_smi_0x88(void)
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{
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{
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const uint32_t status = smi_read32(0x88);
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const uint32_t status = smi_read32(SMI_REG_SMISTS2);
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if (status & SMI_0x88_ACPI_COMMAND) {
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if (status & TYPE_TO_MASK(SMITYPE_SMI_CMD_PORT)) {
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/* Command received via ACPI SMI command port */
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/* Command received via ACPI SMI command port */
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sb_apmc_smi_handler();
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sb_apmc_smi_handler();
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}
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}
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/* Clear events to prevent re-entering SMI if event isn't handled */
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/* Clear events to prevent re-entering SMI if event isn't handled */
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smi_write32(0x88, status);
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smi_write32(SMI_REG_SMISTS2, status);
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}
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}
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static void process_smi_0x8c(void)
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static void process_smi_0x8c(void)
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{
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{
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const uint32_t status = smi_read32(0x8c);
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const uint32_t status = smi_read32(SMI_REG_SMISTS3);
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/* Clear events to prevent re-entering SMI if event isn't handled */
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/* Clear events to prevent re-entering SMI if event isn't handled */
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smi_write32(0x8c, status);
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smi_write32(SMI_REG_SMISTS4, status);
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}
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}
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static void process_smi_0x90(void)
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static void process_smi_0x90(void)
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{
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{
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const uint32_t status = smi_read32(0x90);
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const uint32_t status = smi_read32(SMI_REG_SMISTS4);
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/* Clear events to prevent re-entering SMI if event isn't handled */
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/* Clear events to prevent re-entering SMI if event isn't handled */
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smi_write32(0x90, status);
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smi_write32(SMI_REG_SMISTS4, status);
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}
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}
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void southbridge_smi_handler(void)
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void southbridge_smi_handler(void)
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{
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{
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const uint16_t smi_src = smi_read16(0x94);
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const uint16_t smi_src = smi_read16(SMI_REG_POINTER);
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if (smi_src & SMI_SOURCE_SCI)
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if (smi_src & SMI_STATUS_SRC_SCI)
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process_smi_sci();
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process_smi_sci();
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if (smi_src & SMI_SOURCE_GPE)
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if (smi_src & SMI_STATUS_SRC_0)
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process_gpe_smi();
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process_gpe_smi();
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if (smi_src & SMI_SOURCE_0x84)
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if (smi_src & SMI_STATUS_SRC_1)
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process_smi_0x84();
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process_smi_0x84();
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if (smi_src & SMI_SOURCE_0x88)
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if (smi_src & SMI_STATUS_SRC_2)
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process_smi_0x88();
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process_smi_0x88();
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if (smi_src & SMI_SOURCE_IRQ_TRAP)
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if (smi_src & SMI_STATUS_SRC_3)
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process_smi_0x8c();
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process_smi_0x8c();
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if (smi_src & SMI_SOURCE_0x90)
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if (smi_src & SMI_STATUS_SRC_4)
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process_smi_0x90();
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process_smi_0x90();
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}
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}
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