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soc/intel/cannonlake: Make correct C-state entries for S0ix and non-S0ix 

TEST=Dump SSDT entries to verify _CST between S0ix enable and disable.

Change-Id: I25e8f8c13bb91c2645e8e9fdfdf9ba4d7022f1b1
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/31154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
This commit is contained in:
Ronak Kanabar 2019-01-30 18:53:14 +05:30 committed by Patrick Georgi
parent 003fdcbda2
commit c6c4d00182
1 changed files with 2 additions and 2 deletions
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4
src/soc/intel/cannonlake/acpi.c
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@ -121,13 +121,13 @@ static const acpi_cstate_t cstate_map[NUM_C_STATES] = {
},
};
static int cstate_set_s0ix[] = {
static int cstate_set_non_s0ix[] = {
C_STATE_C1E,
C_STATE_C6_LONG_LAT,
C_STATE_C7S_LONG_LAT
};
static int cstate_set_non_s0ix[] = {
static int cstate_set_s0ix[] = {
C_STATE_C1E,
C_STATE_C7S_LONG_LAT,
C_STATE_C10