From c6d0a4c1a854cb51907bcf67b829954624bcff08 Mon Sep 17 00:00:00 2001
From: David Wu <david_wu@quanta.corp-partner.google.com>
Date: Mon, 13 Jun 2022 17:34:33 +0800
Subject: [PATCH] mb/google/brya/var/kano: Disable PCH USB2 phy power gating

The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for kano board. Please refer Intel doc#723158 for
more information.

BUG=None
TEST=Verify the build for kano board

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I19430a68e1e847e71382781563200a4c88f37a59
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
---
 src/mainboard/google/brya/variants/kano/overridetree.cb | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb
index ad0d0f7749..2a1511ce8d 100644
--- a/src/mainboard/google/brya/variants/kano/overridetree.cb
+++ b/src/mainboard/google/brya/variants/kano/overridetree.cb
@@ -19,6 +19,10 @@ end
 chip soc/intel/alderlake
 	register "sagv" = "SaGv_Enabled"
 
+	# As per Intel Advisory doc#723158, the change is required to prevent possible
+	# display flickering issue.
+	register "usb2_phy_sus_pg_disable" = "1"
+
 	# GPE configuration
 	register "pmc_gpe0_dw1" = "GPP_D"