GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

nb/intel/sandybridge: Do not rewrite write leveling sequence 

There's no need to reprogram the exact same sequence over a hundred
times. Move it out of the timB loop, and drop the `test_timB` function.

Tested on Asus P8H61-M PRO, still boots.

Change-Id: I375e325cf8b5369889b9cb059c3675cd00bdbb3f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Angel Pons 2020-11-14 16:52:33 +01:00 committed by Felix Held
parent 9426721807
commit c6d2feaee5
1 changed files with 14 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

33
src/northbridge/intel/sandybridge/raminit_common.c
View File

@ -1696,24 +1696,6 @@ static void precharge(ramctr_timing *ctrl)
}
}
static void test_timB(ramctr_timing *ctrl, int channel, int slotrank)
{
u32 mr1reg = make_mr1(ctrl, slotrank, channel) | 1 << 7;
int bank = 1;
if (ctrl->rank_mirror[channel][slotrank])
ddr3_mirror_mrreg(&bank, &mr1reg);
wait_for_iosav(channel);
iosav_write_jedec_write_leveling_sequence(ctrl, channel, slotrank, bank, mr1reg);
/* Execute command queue */
iosav_run_once(channel);
wait_for_iosav(channel);
}
static int discover_timB(ramctr_timing *ctrl, int channel, int slotrank)
{
int timB;
@ -1729,13 +1711,26 @@ static int discover_timB(ramctr_timing *ctrl, int channel, int slotrank)
};
MCHBAR32(GDCRTRAININGMOD) = training_mod.raw;
u32 mr1reg = make_mr1(ctrl, slotrank, channel) | 1 << 7;
int bank = 1;
if (ctrl->rank_mirror[channel][slotrank])
ddr3_mirror_mrreg(&bank, &mr1reg);
wait_for_iosav(channel);
iosav_write_jedec_write_leveling_sequence(ctrl, channel, slotrank, bank, mr1reg);
for (timB = 0; timB < 128; timB++) {
FOR_ALL_LANES {
ctrl->timings[channel][slotrank].lanes[lane].timB = timB;
}
program_timings(ctrl, channel);
test_timB(ctrl, channel, slotrank);
/* Execute command queue */
iosav_run_once(channel);
wait_for_iosav(channel);
FOR_ALL_LANES {
statistics[lane][timB] = !((MCHBAR32(lane_base[lane] +