mediatek/mt8173: detect sdram size at runtime

Remove DRAM_SIZE_MB Kconfig setting and use sdram_size_mb() to detect
the DRAM size at runtime.

BUG=chrome-os-partner:49427
BRANCH=none
TEST=Boot to kernel

Change-Id: I0c3245db73335fb4f1c89c1debde715fc96ecba7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 00f6f2bbed0e7d23181337b9274191b31e73e223
Original-Change-Id: I409163fe527e966c184f28d7d9bbc809ae2308ed
Original-Signed-off-by: PH Hsu <ph.hsu@mediatek.com>
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/327961
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/331176
Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13988
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/mainboard/google/oak/Kconfig

@@ -41,10 +41,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "oak"
 
-config DRAM_SIZE_MB
-	int
-	default 2048
-
 config EC_GOOGLE_CHROMEEC_SPI_BUS
 	hex
 	default 0

src/soc/mediatek/mt8173/Makefile.inc

@@ -59,7 +59,7 @@ romstage-y += rtc.c
 
 ################################################################################
 
-ramstage-y += cbmem.c
+ramstage-y += cbmem.c emi.c
 ramstage-y += spi.c
 ramstage-$(CONFIG_SPI_FLASH) += flash_controller.c
 ramstage-y += soc.c mtcmos.c

src/soc/mediatek/mt8173/cbmem.c

@@ -17,9 +17,9 @@
 #include <stddef.h>
 #include <stdlib.h>
 #include <symbols.h>
+#include <soc/emi.h>
 
 void *cbmem_top(void)
 {
-	return (void *)min((uintptr_t)_dram + ((size_t)CONFIG_DRAM_SIZE_MB * MiB),
-			   (uintptr_t)4 * GiB);
+	return (void *)min((uintptr_t)_dram + sdram_size(), (uintptr_t)4 * GiB);
 }

src/soc/mediatek/mt8173/emi.c

@@ -127,6 +127,42 @@ static void init_dram(const struct mt8173_sdram_params *sdram_params)
 	dramc_init(CHANNEL_B, sdram_params);
 }
 
+size_t sdram_size(void)
+{
+	u32 value = read32(&emi_regs->emi_cona);
+	u32 bit_counter = 0;
+
+	/* check if dual channel */
+	if (value & CONA_DUAL_CH_EN)
+		bit_counter++;
+
+	/* check if 32bit , 32 = 2^5*/
+	if (value & CONA_32BIT_EN)
+		bit_counter += 5;
+	else
+		bit_counter += 4;
+
+	/* check column address */
+	/* 00 is 9 bits, 01 is 10 bits , 10 is 11 bits */
+	bit_counter += ((value & COL_ADDR_BITS_MASK) >> COL_ADDR_BITS_SHIFT) +
+		       9;
+
+	/* check if row address */
+	/*00 is 13 bits , 01 is 14 bits , 10 is 15bits , 11 is 16 bits */
+	bit_counter += ((value & ROW_ADDR_BITS_MASK) >> ROW_ADDR_BITS_SHIFT) +
+		       13;
+
+	/* check if dual rank */
+	if (value & CONA_DUAL_RANK_EN)
+		bit_counter++;
+
+	/* add bank address bit, LPDDR3 is 8 banks =2^3 */
+	bit_counter += 3;
+
+	/*transfor bits to bytes */
+	return ((size_t)1 << (bit_counter - 3));
+}
+
 void mt_set_emi(const struct mt8173_sdram_params *sdram_params)
 {
 	/* voltage info */

src/soc/mediatek/mt8173/include/soc/emi.h

@@ -18,6 +18,7 @@
 
 #include <soc/dramc_common.h>
 #include <stdint.h>
+#include <types.h>
 
 /* DDR type */
 enum ram_type {
@@ -124,6 +125,17 @@ struct mt8173_mrs_params {
 	u32 mrs_63;
 };
 
+enum {
+	/* CONA = 0x000 */
+	CONA_DUAL_CH_EN  = BIT(0),
+	CONA_32BIT_EN  = BIT(1),
+	CONA_DUAL_RANK_EN  = BIT(17),
+	COL_ADDR_BITS_SHIFT = 4,
+	COL_ADDR_BITS_MASK = 3 << COL_ADDR_BITS_SHIFT,
+	ROW_ADDR_BITS_SHIFT = 12,
+	ROW_ADDR_BITS_MASK = 3 << ROW_ADDR_BITS_SHIFT
+};
+
 struct mt8173_sdram_params {
 	struct mt8173_calib_params calib_params;
 	struct mt8173_timing_params ac_timing;
@@ -136,5 +148,5 @@ struct mt8173_sdram_params {
 void mt_set_emi(const struct mt8173_sdram_params *sdram_params);
 void mt_mem_init(const struct mt8173_sdram_params *sdram_params);
 const struct mt8173_sdram_params *get_sdram_config(void);
-
+size_t sdram_size(void);
 #endif

src/soc/mediatek/mt8173/mmu_operations.c

@@ -20,12 +20,11 @@
 #include <stdlib.h>
 #include <stdint.h>
 #include <soc/addressmap.h>
+#include <soc/emi.h>
 #include <soc/infracfg.h>
 #include <soc/mcucfg.h>
 #include <soc/mmu_operations.h>
 
-static const uint64_t dram_size = (uint64_t)CONFIG_DRAM_SIZE_MB * MiB;
-
 void mt8173_mmu_init(void)
 {
 	mmu_init();
@@ -48,7 +47,7 @@ void mt8173_mmu_init(void)
 void mt8173_mmu_after_dram(void)
 {
 	/* Map DRAM as cached now that it's up and running */
-	mmu_config_range(_dram, dram_size, CACHED_MEM);
+	mmu_config_range(_dram, (uintptr_t)sdram_size(), CACHED_MEM);
 
 	/* Unmap L2C SRAM so it can be reclaimed by L2 cache */
 	/* TODO: Implement true unmapping, and also use it for the zero-page! */

src/soc/mediatek/mt8173/soc.c

@@ -17,11 +17,11 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <symbols.h>
+#include <soc/emi.h>
 
 static void soc_read_resources(device_t dev)
 {
-	ram_resource(dev, 0, (uintptr_t)_dram / KiB,
-		     CONFIG_DRAM_SIZE_MB * (MiB / KiB));
+	ram_resource(dev, 0, (uintptr_t)_dram / KiB, sdram_size() / KiB);
 }
 
 static void soc_init(device_t dev)