soc/amd/picasso: Relocate FSP-M to address in DRAM
On Picasso, DRAM is up by the time FSP-M runs. This change relocates FSP-M binary to a specific address (0x90000000) in DRAM. Currently, this address is randomly chosen to ensure it does not overlap any of the other stages. Once we have a unified memory map set up for Picasso, this address can be updated along with it. BUG=b:155322763,b:150746858,b:152909132 Change-Id: I1a49765f00de9f97fa3dbd5bc288a3ed0d7087f6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41828 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -228,6 +228,10 @@ config MAINBOARD_POWER_RESTORE
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return to S0. Otherwise the system will remain in S5 once power
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is restored.
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config FSP_M_ADDR
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hex
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default 0x90000000
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config X86_RESET_VECTOR
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hex
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default 0x807fff0
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@ -458,4 +458,6 @@ apu/amdfw-type := raw
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endif # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y)
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$(call strip_quotes,$(CONFIG_FSP_M_CBFS))-options := -b $(CONFIG_FSP_M_ADDR)
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endif # ($(CONFIG_SOC_AMD_PICASSO),y)
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