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mb/google/nissa/var/xivu: Update DPTF parameters 

Follow thermal table from thermal team.

1. Modify TS1 passive policy to 68.

BUG=b:249446156
TEST=emerge-nissa coreboot chromeos-bootimage

Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I8539a29cab4863034a2b64d38aef4b772473246d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69960
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Ian Feng 2022-11-24 10:49:35 +08:00 committed by Felix Held
parent 68fb5437f9
commit c6e6d0d522
1 changed files with 1 additions and 1 deletions
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src/mainboard/google/brya/variants/xivu/overridetree.cb
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@ -107,7 +107,7 @@ chip soc/intel/alderlake
register "policies.passive" = "{
[0] = DPTF_PASSIVE(CPU, CPU, 90, 5000),
[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 77, 5000),
[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 60, 5000),
[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 68, 5000),
[3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 78, 5000),
}"