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vc/mediatek/mt8195: Improve settings of duty calibration 

Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: Ic4aeaec947356001d073df72977899ca06b18bda
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This commit is contained in:
Ryan Chuang 2021-07-06 17:12:27 +08:00 committed by Patrick Georgi
parent e53cbfdbf4
commit c6ed254835
2 changed files with 18 additions and 10 deletions
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26
src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c
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@ -14804,18 +14804,26 @@ void DramcNewDutyCalibration(DRAMC_CTX_T *p)
#endif #endif
#endif #endif
{ {
U8 u1ChannelIdx;
U8 u1backup_channel = vGetPHY2ChannelMapping(p);
#if SUPPORT_SAVE_TIME_FOR_CALIBRATION #if SUPPORT_SAVE_TIME_FOR_CALIBRATION
if(p->femmc_Ready==1) if(p->femmc_Ready==1)
{ {
DramcClockDutySetClkDelayCell(p, p->pSavetimeData->s1ClockDuty_clk_delay_cell[p->channel]); for(u1ChannelIdx=CHANNEL_A; u1ChannelIdx<p->support_channel_num; u1ChannelIdx++){
DQSDutyScan_SetDqsDelayCell(p, p->pSavetimeData->s1DQSDuty_clk_delay_cell[p->channel]); vSetPHY2ChannelMapping(p, u1ChannelIdx);
#if __LP5_COMBO__
WCKDutyScan_SetWCKDelayCell(p, p->pSavetimeData->s1WCKDuty_clk_delay_cell[p->channel]); DramcClockDutySetClkDelayCell(p, p->pSavetimeData->s1ClockDuty_clk_delay_cell[p->channel]);
#endif DQSDutyScan_SetDqsDelayCell(p, p->pSavetimeData->s1DQSDuty_clk_delay_cell[p->channel]);
#if APPLY_DQDQM_DUTY_CALIBRATION #if __LP5_COMBO__
DQDQMDutyScan_SetDQDQMDelayCell(p, p->channel, p->pSavetimeData->s1DQMDuty_clk_delay_cell[p->channel], DutyScan_Calibration_K_DQM); WCKDutyScan_SetWCKDelayCell(p, p->pSavetimeData->s1WCKDuty_clk_delay_cell[p->channel]);
DQDQMDutyScan_SetDQDQMDelayCell(p, p->channel, p->pSavetimeData->s1DQDuty_clk_delay_cell[p->channel], DutyScan_Calibration_K_DQ); #endif
#endif #if APPLY_DQDQM_DUTY_CALIBRATION
DQDQMDutyScan_SetDQDQMDelayCell(p, p->channel, p->pSavetimeData->s1DQMDuty_clk_delay_cell[p->channel], DutyScan_Calibration_K_DQM);
DQDQMDutyScan_SetDQDQMDelayCell(p, p->channel, p->pSavetimeData->s1DQDuty_clk_delay_cell[p->channel], DutyScan_Calibration_K_DQ);
#endif
}
vSetPHY2ChannelMapping(p, u1backup_channel);
vSetCalibrationResult(p, DRAM_CALIBRATION_DUTY_SCAN, DRAM_FAST_K); vSetCalibrationResult(p, DRAM_CALIBRATION_DUTY_SCAN, DRAM_FAST_K);
return; return;

2
src/vendorcode/mediatek/mt8195/include/dramc_pi_api.h
View File

@ -123,7 +123,7 @@
#else #else
#define ENABLE_EYESCAN_GRAPH 1 #define ENABLE_EYESCAN_GRAPH 1
#endif #endif
#define EYESCAN_GRAPH_CATX_VREF_STEP 1 // 1 (origin), 2 (div 2)(save 9K size), 5 for A60868 #define EYESCAN_GRAPH_CATX_VREF_STEP 0x1U // 1 (origin), 2 (div 2)(save 9K size), 5 for A60868
#define EYESCAN_GRAPH_RX_VREF_STEP 2 #define EYESCAN_GRAPH_RX_VREF_STEP 2
#define EYESCAN_RX_VREF_RANGE_END 128 //field is 6 bit, but can only use 0~63,7bit ->127 #define EYESCAN_RX_VREF_RANGE_END 128 //field is 6 bit, but can only use 0~63,7bit ->127
#define EYESCAN_SKIP_UNTERM_CBT_EYESCAN_VREF 10 #define EYESCAN_SKIP_UNTERM_CBT_EYESCAN_VREF 10