vc/mediatek/mt8195: Improve settings of duty calibration
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: Ic4aeaec947356001d073df72977899ca06b18bda Reviewed-on: https://review.coreboot.org/c/coreboot/+/56104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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@ -14804,9 +14804,15 @@ void DramcNewDutyCalibration(DRAMC_CTX_T *p)
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#endif
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#endif
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{
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U8 u1ChannelIdx;
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U8 u1backup_channel = vGetPHY2ChannelMapping(p);
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#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
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if(p->femmc_Ready==1)
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{
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for(u1ChannelIdx=CHANNEL_A; u1ChannelIdx<p->support_channel_num; u1ChannelIdx++){
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vSetPHY2ChannelMapping(p, u1ChannelIdx);
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DramcClockDutySetClkDelayCell(p, p->pSavetimeData->s1ClockDuty_clk_delay_cell[p->channel]);
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DQSDutyScan_SetDqsDelayCell(p, p->pSavetimeData->s1DQSDuty_clk_delay_cell[p->channel]);
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#if __LP5_COMBO__
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@ -14816,6 +14822,8 @@ void DramcNewDutyCalibration(DRAMC_CTX_T *p)
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DQDQMDutyScan_SetDQDQMDelayCell(p, p->channel, p->pSavetimeData->s1DQMDuty_clk_delay_cell[p->channel], DutyScan_Calibration_K_DQM);
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DQDQMDutyScan_SetDQDQMDelayCell(p, p->channel, p->pSavetimeData->s1DQDuty_clk_delay_cell[p->channel], DutyScan_Calibration_K_DQ);
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#endif
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}
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vSetPHY2ChannelMapping(p, u1backup_channel);
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vSetCalibrationResult(p, DRAM_CALIBRATION_DUTY_SCAN, DRAM_FAST_K);
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return;
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@ -123,7 +123,7 @@
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#else
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#define ENABLE_EYESCAN_GRAPH 1
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#endif
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#define EYESCAN_GRAPH_CATX_VREF_STEP 1 // 1 (origin), 2 (div 2)(save 9K size), 5 for A60868
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#define EYESCAN_GRAPH_CATX_VREF_STEP 0x1U // 1 (origin), 2 (div 2)(save 9K size), 5 for A60868
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#define EYESCAN_GRAPH_RX_VREF_STEP 2
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#define EYESCAN_RX_VREF_RANGE_END 128 //field is 6 bit, but can only use 0~63,7bit ->127
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#define EYESCAN_SKIP_UNTERM_CBT_EYESCAN_VREF 10
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