mb/google/brya/variants/brya0: set power limits for thermal

Set power limits for brya0 variant board based on CPU SKUs
which is detectable at runtime.

BUG=b:194745919
BRANCH=None
TEST=Build FW and test on brya0 variant board with below messages,
 On brya (282):
  Overriding DPTF power limits PL1 (3000, 15000) PL2 (39000, 39000)
 On brya (482):
  Overriding DPTF power limits PL1 (4000, 28000) PL2 (43000, 43000)

Change-Id: I4c07319af756b10e5d22f320e97ff956fb4a14c6
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56622
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/brya/variants/brya0/Makefile.inc

@@ -2,3 +2,4 @@ bootblock-y += gpio.c
 ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
 ramstage-$(CONFIG_FW_CONFIG) += variant.c
 ramstage-y += gpio.c
+ramstage-y += ramstage.c

src/mainboard/google/brya/variants/brya0/ramstage.c

@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <device/pci_ids.h>
+
+const struct cpu_power_limits limits[] = {
+	/* SKU_ID, pl1_min, pl1_max, pl2_min, pl2_max */
+	/* PL2 values are for baseline config as per bug:191906315 comment #10 */
+	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 3000, 15000, 39000, 39000 },
+	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 4000, 28000, 43000, 43000 },
+	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 5000, 45000, 80000, 80000 },
+};
+
+void variant_devtree_update(void)
+{
+	size_t total_entries = ARRAY_SIZE(limits);
+	variant_update_power_limits(limits, total_entries);
+}