GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Support for nehalem northbridge 

Including raminit

Change-Id: If1dd3855181481b8b928adf0fdb40b29d15897db
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4044
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Vladimir Serbinenko 2013-11-12 22:32:08 +01:00
parent 888d559b03
commit c6f6be0929
22 changed files with 11398 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/cpu/x86/smm/smmhandler_tseg.S
View File

@ -60,6 +60,9 @@
#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE #if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG) #define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG)
#elif CONFIG_NORTHBRIDGE_INTEL_NEHALEM
#include <northbridge/intel/nehalem/nehalem.h>
#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG)
#elif CONFIG_NORTHBRIDGE_INTEL_HASWELL #elif CONFIG_NORTHBRIDGE_INTEL_HASWELL
#include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/haswell.h>
#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG) #define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG)

3
src/cpu/x86/smm/smmrelocate.S
View File

@ -48,6 +48,9 @@
#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE #if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG) #define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG)
#elif CONFIG_NORTHBRIDGE_INTEL_NEHALEM
#include <northbridge/intel/nehalem/nehalem.h>
#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG)
#else #else
#error "Northbridge must define TSEG_BAR." #error "Northbridge must define TSEG_BAR."
#endif #endif

1
src/northbridge/intel/Kconfig
View File

@ -12,5 +12,6 @@ source src/northbridge/intel/i945/Kconfig
source src/northbridge/intel/gm45/Kconfig source src/northbridge/intel/gm45/Kconfig
source src/northbridge/intel/sch/Kconfig source src/northbridge/intel/sch/Kconfig
source src/northbridge/intel/i5000/Kconfig source src/northbridge/intel/i5000/Kconfig
source src/northbridge/intel/nehalem/Kconfig
source src/northbridge/intel/sandybridge/Kconfig source src/northbridge/intel/sandybridge/Kconfig
source src/northbridge/intel/haswell/Kconfig source src/northbridge/intel/haswell/Kconfig

1
src/northbridge/intel/Makefile.inc
View File

@ -12,6 +12,7 @@ subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945) += i945
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_GM45) += gm45 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_GM45) += gm45
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SCH) += sch subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SCH) += sch
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I5000) += i5000 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I5000) += i5000
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_NEHALEM) += nehalem
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += sandybridge subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += sandybridge
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += sandybridge subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += sandybridge
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell

60
src/northbridge/intel/nehalem/Kconfig Normal file
View File

@ -0,0 +1,60 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2010 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
config NORTHBRIDGE_INTEL_NEHALEM
bool
select CPU_INTEL_MODEL_2065X
select MMCONF_SUPPORT
select MMCONF_SUPPORT_DEFAULT
select VGA
if NORTHBRIDGE_INTEL_NEHALEM
config VGA_BIOS_ID
string
default "8086,0046"
config DCACHE_RAM_BASE
hex
default 0xff7f0000
config DCACHE_RAM_SIZE
hex
default 0x10000
config BOOTBLOCK_NORTHBRIDGE_INIT
string
default "northbridge/intel/nehalem/bootblock.c"
config TRAINING_CACHE_SIZE
hex
default 0x10000
config CBFS_SIZE
hex "Size of CBFS filesystem in ROM"
default 0x100000
help
On Nehalem systems the firmware image has to
store a lot more than just coreboot, including:
- a firmware descriptor
- Intel Management Engine firmware
This option allows to limit the size of the CBFS portion in the
firmware image.
endif

43
src/northbridge/intel/nehalem/Makefile.inc Normal file
View File

@ -0,0 +1,43 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2010 Google Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
ramstage-y += northbridge.c
ramstage-y += gma.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
ramstage-y += ../sandybridge/mrccache.c
romstage-y += raminit.c
romstage-y += early_init.c
romstage-y += ../sandybridge/mrccache.c
romstage-y += ../../../arch/x86/lib/walkcbfs.S
smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
$(obj)/mrc.cache:
dd if=/dev/zero count=1 \
bs=$(shell printf "%d" $(CONFIG_TRAINING_CACHE_SIZE) ) | \
tr '\000' '\377' > $@
cbfs-files-y += mrc.cache
mrc.cache-file := $(obj)/mrc.cache
mrc.cache-position := 0xfff80000
mrc.cache-type := 0xac
$(obj)/northbridge/intel/nehalem/acpi.ramstage.o : $(obj)/build.h

198
src/northbridge/intel/nehalem/acpi.c Normal file
View File

@ -0,0 +1,198 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2012 The Chromium OS Authors
* Copyright (C) 2013 Vladimir Serbinenko
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include <types.h>
#include <string.h>
#include <console/console.h>
#include <arch/io.h>
#include <arch/acpi.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <build.h>
#include "nehalem.h"
unsigned long acpi_fill_mcfg(unsigned long current)
{
u32 pciexbar = 0;
u32 pciexbar_reg;
int max_buses;
/* Quickpath bus is not in standard coreboot device tree,
so read register directly. */
pciexbar_reg = read32(DEFAULT_PCIEXBAR
| (QUICKPATH_BUS << 20) | 0x1050);
// MMCFG not supported or not enabled.
if (!(pciexbar_reg & (1 << 0)))
return current;
switch ((pciexbar_reg >> 1) & 3) {
case 0: // 256MB
pciexbar =
pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
(1 << 28));
max_buses = 256;
break;
case 1: // 128M
pciexbar =
pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
(1 << 28) | (1 << 27));
max_buses = 128;
break;
case 2: // 64M
pciexbar =
pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
(1 << 28) | (1 << 27) | (1 << 26));
max_buses = 64;
break;
default: // RSVD
return current;
}
if (!pciexbar)
return current;
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current,
pciexbar, 0x0, 0x0, max_buses - 1);
return current;
}
static void *get_intel_vbios(void)
{
/* This should probably be looking at CBFS or we should always
* deploy the VBIOS on Intel systems, even if we don't run it
* in coreboot (e.g. SeaBIOS only scenarios).
*/
u8 *vbios = (u8 *) 0xc0000;
optionrom_header_t *oprom = (optionrom_header_t *) vbios;
optionrom_pcir_t *pcir = (optionrom_pcir_t *) (vbios +
oprom->pcir_offset);
printk(BIOS_DEBUG, "GET_VBIOS: %x %x %x %x %x\n",
oprom->signature, pcir->vendor, pcir->classcode[0],
pcir->classcode[1], pcir->classcode[2]);
if ((oprom->signature == OPROM_SIGNATURE) &&
(pcir->vendor == PCI_VENDOR_ID_INTEL) &&
(pcir->classcode[0] == 0x00) &&
(pcir->classcode[1] == 0x00) && (pcir->classcode[2] == 0x03))
return (void *)vbios;
return NULL;
}
static int init_opregion_vbt(igd_opregion_t * opregion)
{
void *vbios;
vbios = get_intel_vbios();
if (!vbios) {
printk(BIOS_DEBUG, "VBIOS not found.\n");
return 1;
}
printk(BIOS_DEBUG, " ... VBIOS found at %p\n", vbios);
optionrom_header_t *oprom = (optionrom_header_t *) vbios;
optionrom_vbt_t *vbt = (optionrom_vbt_t *) (vbios + oprom->vbt_offset);
if (read32((unsigned long)vbt->hdr_signature) != VBT_SIGNATURE) {
printk(BIOS_DEBUG, "VBT not found!\n");
return 1;
}
memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, 4);
memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size < 7168 ?
vbt->hdr_vbt_size : 7168);
return 0;
}
/* Initialize IGD OpRegion, called from ACPI code */
int init_igd_opregion(igd_opregion_t * opregion)
{
device_t igd;
u16 reg16;
memset((void *)opregion, 0, sizeof(igd_opregion_t));
// FIXME if IGD is disabled, we should exit here.
memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE,
sizeof(IGD_OPREGION_SIGNATURE));
/* 8kb */
opregion->header.size = sizeof(igd_opregion_t) / 1024;
opregion->header.version = IGD_OPREGION_VERSION;
// FIXME We just assume we're mobile for now
opregion->header.mailboxes = MAILBOXES_MOBILE;
// TODO Initialize Mailbox 1
// TODO Initialize Mailbox 3
opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS;
opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH;
opregion->mailbox3.pcft = 0; // should be (IMON << 1) & 0x3e
opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS;
opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000;
opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19;
opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433;
opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c;
opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866;
opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f;
opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99;
opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2;
opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc;
opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5;
opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff;
init_opregion_vbt(opregion);
/* TODO This needs to happen in S3 resume, too.
* Maybe it should move to the finalize handler
*/
igd = dev_find_slot(0, PCI_DEVFN(0x2, 0));
pci_write_config32(igd, ASLS, (u32) opregion);
reg16 = pci_read_config16(igd, SWSCI);
reg16 &= ~(1 << 0);
reg16 |= (1 << 15);
pci_write_config16(igd, SWSCI, reg16);
/* clear dmisci status */
reg16 = inw(DEFAULT_PMBASE + TCO1_STS);
reg16 |= DMISCI_STS; // reference code does an &=
outw(DEFAULT_PMBASE + TCO1_STS, reg16);
/* clear acpi tco status */
outl(DEFAULT_PMBASE + GPE0_STS, TCOSCI_STS);
/* enable acpi tco scis */
reg16 = inw(DEFAULT_PMBASE + GPE0_EN);
reg16 |= TCOSCI_EN;
outw(DEFAULT_PMBASE + GPE0_EN, reg16);
return 0;
}

350
src/northbridge/intel/nehalem/acpi/hostbridge.asl Normal file
View File

@ -0,0 +1,350 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
Name(_HID,EISAID("PNP0A08")) // PCIe
Name(_CID,EISAID("PNP0A03")) // PCI
Name(_ADR, 0)
Name(_BBN, 0)
Device (MCHC)
{
Name(_ADR, 0x00000000) // 0:0.0
OperationRegion(MCHP, PCI_Config, 0x00, 0x100)
Field (MCHP, DWordAcc, NoLock, Preserve)
{
Offset (0x40), // EPBAR
EPEN, 1, // Enable
, 11, //
EPBR, 24, // EPBAR
Offset (0x48), // MCHBAR
MHEN, 1, // Enable
, 13, //
MHBR, 22, // MCHBAR
Offset (0x60), // PCIe BAR
PXEN, 1, // Enable
PXSZ, 2, // BAR size
, 23, //
PXBR, 10, // PCIe BAR
Offset (0x68), // DMIBAR
DMEN, 1, // Enable
, 11, //
DMBR, 24, // DMIBAR
Offset (0xa0),
TOM, 16,
TUUD, 16,
Offset (0xb0), // Top of Low Used Memory
TLUD, 16,
}
Mutex (CTCM, 1) /* CTDP Switch Mutex (sync level 1) */
Name (CTCC, 0) /* CTDP Current Selection */
Name (CTCN, 0) /* CTDP Nominal Select */
Name (CTCD, 1) /* CTDP Down Select */
Name (CTCU, 2) /* CTDP Up Select */
OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR, 0x8000)
Field (MCHB, DWordAcc, Lock, Preserve)
{
Offset (0x5930),
CTDN, 15, /* CTDP Nominal PL1 */
Offset (0x59a0),
PL1V, 15, /* Power Limit 1 Value */
PL1E, 1, /* Power Limit 1 Enable */
PL1C, 1, /* Power Limit 1 Clamp */
PL1T, 7, /* Power Limit 1 Time */
Offset (0x59a4),
PL2V, 15, /* Power Limit 2 Value */
PL2E, 1, /* Power Limit 2 Enable */
PL2C, 1, /* Power Limit 2 Clamp */
PL2T, 7, /* Power Limit 2 Time */
Offset (0x5f3c),
TARN, 8, /* CTDP Nominal Turbo Activation Ratio */
Offset (0x5f40),
CTDD, 15, /* CTDP Down PL1 */
, 1,
TARD, 8, /* CTDP Down Turbo Activation Ratio */
Offset (0x5f48),
CTDU, 15, /* CTDP Up PL1 */
, 1,
TARU, 8, /* CTDP Up Turbo Activation Ratio */
Offset (0x5f50),
CTCS, 2, /* CTDP Select */
Offset (0x5f54),
TARS, 8, /* Turbo Activation Ratio Select */
}
/*
* Search CPU0 _PSS looking for control=arg0 and then
* return previous P-state entry number for new _PPC
*
* Format of _PSS:
* Name (_PSS, Package () {
* Package (6) { freq, power, tlat, blat, control, status }
* }
*/
External (\_PR.CPU0._PSS)
Method (PSSS, 1, NotSerialized)
{
Store (One, Local0) /* Start at P1 */
Store (SizeOf (\_PR.CPU0._PSS), Local1)
While (LLess (Local0, Local1)) {
/* Store _PSS entry Control value to Local2 */
ShiftRight (DeRefOf (Index (DeRefOf (Index
(\_PR.CPU0._PSS, Local0)), 4)), 8, Local2)
If (LEqual (Local2, Arg0)) {
Return (Subtract (Local0, 1))
}
Increment (Local0)
}
Return (0)
}
/* Set TDP Down */
Method (STND, 0, Serialized)
{
If (Acquire (CTCM, 100)) {
Return (0)
}
If (LEqual (CTCD, CTCC)) {
Release (CTCM)
Return (0)
}
Store ("Set TDP Down", Debug)
/* Set CTC */
Store (CTCD, CTCS)
/* Set TAR */
Store (TARD, TARS)
/* Set PPC limit and notify OS */
Store (PSSS (TARD), PPCM)
PPCN ()
/* Set PL2 to 1.25 * PL1 */
Divide (Multiply (CTDD, 125), 100, Local0, PL2V)
/* Set PL1 */
Store (CTDD, PL1V)
/* Store the new TDP Down setting */
Store (CTCD, CTCC)
Release (CTCM)
Return (1)
}
/* Set TDP Nominal from Down */
Method (STDN, 0, Serialized)
{
If (Acquire (CTCM, 100)) {
Return (0)
}
If (LEqual (CTCN, CTCC)) {
Release (CTCM)
Return (0)
}
Store ("Set TDP Nominal", Debug)
/* Set PL1 */
Store (CTDN, PL1V)
/* Set PL2 to 1.25 * PL1 */
Divide (Multiply (CTDN, 125), 100, Local0, PL2V)
/* Set PPC limit and notify OS */
Store (PSSS (TARN), PPCM)
PPCN ()
/* Set TAR */
Store (TARN, TARS)
/* Set CTC */
Store (CTCN, CTCS)
/* Store the new TDP Nominal setting */
Store (CTCN, CTCC)
Release (CTCM)
Return (1)
}
}
// Current Resource Settings
Method (_CRS, 0, Serialized)
{
Name (MCRS, ResourceTemplate()
{
// Bus Numbers
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00)
// IO Region 0
DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00)
// PCI Config Space
Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
// IO Region 1
DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01)
// VGA memory (0xa0000-0xbffff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
0x00020000,,, ASEG)
// OPROM reserved (0xc0000-0xc3fff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
0x00004000,,, OPR0)
// OPROM reserved (0xc4000-0xc7fff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
0x00004000,,, OPR1)
// OPROM reserved (0xc8000-0xcbfff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
0x00004000,,, OPR2)
// OPROM reserved (0xcc000-0xcffff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
0x00004000,,, OPR3)
// OPROM reserved (0xd0000-0xd3fff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
0x00004000,,, OPR4)
// OPROM reserved (0xd4000-0xd7fff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
0x00004000,,, OPR5)
// OPROM reserved (0xd8000-0xdbfff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
0x00004000,,, OPR6)
// OPROM reserved (0xdc000-0xdffff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
0x00004000,,, OPR7)
// BIOS Extension (0xe0000-0xe3fff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
0x00004000,,, ESG0)
// BIOS Extension (0xe4000-0xe7fff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
0x00004000,,, ESG1)
// BIOS Extension (0xe8000-0xebfff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
0x00004000,,, ESG2)
// BIOS Extension (0xec000-0xeffff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000ec000, 0x000effff, 0x00000000,
0x00004000,,, ESG3)
// System BIOS (0xf0000-0xfffff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
0x00010000,,, FSEG)
// PCI Memory Region (Top of memory-0xfebfffff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x00000000, 0xfebfffff, 0x00000000,
0xfec00000,,, PM01)
// TPM Area (0xfed40000-0xfed44fff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0xfed40000, 0xfed44fff, 0x00000000,
0x00005000,,, TPMR)
})
// Find PCI resource area in MCRS
CreateDwordField(MCRS, PM01._MIN, PMIN)
CreateDwordField(MCRS, PM01._MAX, PMAX)
CreateDwordField(MCRS, PM01._LEN, PLEN)
// Fix up PCI memory region
// Start with Top of Lower Usable DRAM
Store (^MCHC.TLUD, Local0)
ShiftRight (Local0, 4, Local0)
Store (^MCHC.TUUD, Local1)
// Check if ME base is equal
If (LEqual (Local0, Local1)) {
// Use Top Of Memory instead
Store (^MCHC.TOM, Local0)
ShiftRight (Local0, 6, Local0)
}
ShiftLeft (Local0, 20, Local0)
Store (Local0, PMIN)
Add(Subtract(PMAX, PMIN), 1, PLEN)
Return (MCRS)
}
/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */
#include "acpi/nehalem_pci_irqs.asl"

341
src/northbridge/intel/nehalem/acpi/igd.asl Normal file
View File

@ -0,0 +1,341 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
Device (GFX0)
{
Name (_ADR, 0x00020000)
OperationRegion (GFXC, PCI_Config, 0x00, 0x0100)
Field (GFXC, DWordAcc, NoLock, Preserve)
{
Offset (0x10),
BAR0, 64
}
OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000)
Field (GFRG, DWordAcc, NoLock, Preserve)
{
Offset (0x48254),
BCLV, 16,
Offset (0xc8250),
CR1, 32,
CR2, 32
}
/* Display Output Switching */
Method (_DOS, 1)
{
/* Windows 2000 and Windows XP call _DOS to enable/disable
* Display Output Switching during init and while a switch
* is already active
*/
Store (And(Arg0, 7), DSEN)
}
/* We try to support as many i945 systems as possible,
* so keep the number of DIDs flexible.
*/
Method (_DOD, 0)
{
If (LEqual(NDID, 1)) {
Name(DOD1, Package() {
0xffffffff
})
Store (Or(0x00010000, DID1), Index(DOD1, 0))
Return(DOD1)
}
If (LEqual(NDID, 2)) {
Name(DOD2, Package() {
0xffffffff,
0xffffffff
})
Store (Or(0x00010000, DID2), Index(DOD2, 0))
Store (Or(0x00010000, DID2), Index(DOD2, 1))
Return(DOD2)
}
If (LEqual(NDID, 3)) {
Name(DOD3, Package() {
0xffffffff,
0xffffffff,
0xffffffff
})
Store (Or(0x00010000, DID3), Index(DOD3, 0))
Store (Or(0x00010000, DID3), Index(DOD3, 1))
Store (Or(0x00010000, DID3), Index(DOD3, 2))
Return(DOD3)
}
If (LEqual(NDID, 4)) {
Name(DOD4, Package() {
0xffffffff,
0xffffffff,
0xffffffff,
0xffffffff
})
Store (Or(0x00010000, DID4), Index(DOD4, 0))
Store (Or(0x00010000, DID4), Index(DOD4, 1))
Store (Or(0x00010000, DID4), Index(DOD4, 2))
Store (Or(0x00010000, DID4), Index(DOD4, 3))
Return(DOD4)
}
If (LGreater(NDID, 4)) {
Name(DOD5, Package() {
0xffffffff,
0xffffffff,
0xffffffff,
0xffffffff,
0xffffffff
})
Store (Or(0x00010000, DID5), Index(DOD5, 0))
Store (Or(0x00010000, DID5), Index(DOD5, 1))
Store (Or(0x00010000, DID5), Index(DOD5, 2))
Store (Or(0x00010000, DID5), Index(DOD5, 3))
Store (Or(0x00010000, DID5), Index(DOD5, 4))
Return(DOD5)
}
/* Some error happened, but we have to return something */
Return (Package() {0x00000400})
}
Device(DD01)
{
/* Device Unique ID */
Method(_ADR, 0, Serialized)
{
If(LEqual(DID1, 0)) {
Return (1)
} Else {
Return (And(0xffff, DID1))
}
}
/* Device Current Status */
Method(_DCS, 0)
{
TRAP(1)
If (And(CSTE, 1)) {
Return (0x1f)
}
Return(0x1d)
}
/* Query Device Graphics State */
Method(_DGS, 0)
{
If (And(NSTE, 1)) {
Return(1)
}
Return(0)
}
/* Device Set State */
Method(_DSS, 1)
{
/* If Parameter Arg0 is (1 << 31) | (1 << 30), the
* display switch was completed
*/
If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
Store (NSTE, CSTE)
}
}
}
Device(DD02)
{
/* Device Unique ID */
Method(_ADR, 0, Serialized)
{
If(LEqual(DID2, 0)) {
Return (2)
} Else {
Return (And(0xffff, DID2))
}
}
/* Device Current Status */
Method(_DCS, 0)
{
TRAP(1)
If (And(CSTE, 2)) {
Return (0x1f)
}
Return(0x1d)
}
/* Query Device Graphics State */
Method(_DGS, 0)
{
If (And(NSTE, 2)) {
Return(1)
}
Return(0)
}
/* Device Set State */
Method(_DSS, 1)
{
/* If Parameter Arg0 is (1 << 31) | (1 << 30), the
* display switch was completed
*/
If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
Store (NSTE, CSTE)
}
}
}
Device(DD03)
{
/* Device Unique ID */
Method(_ADR, 0, Serialized)
{
If(LEqual(DID3, 0)) {
Return (3)
} Else {
Return (And(0xffff, DID3))
}
}
/* Device Current Status */
Method(_DCS, 0)
{
TRAP(1)
If (And(CSTE, 4)) {
Return (0x1f)
}
Return(0x1d)
}
/* Query Device Graphics State */
Method(_DGS, 0)
{
If (And(NSTE, 4)) {
Return(1)
}
Return(0)
}
/* Device Set State */
Method(_DSS, 1)
{
/* If Parameter Arg0 is (1 << 31) | (1 << 30), the
* display switch was completed
*/
If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
Store (NSTE, CSTE)
}
}
}
Device(DD04)
{
/* Device Unique ID */
Method(_ADR, 0, Serialized)
{
If(LEqual(DID4, 0)) {
Return (4)
} Else {
Return (And(0xffff, DID4))
}
}
/* Device Current Status */
Method(_DCS, 0)
{
TRAP(1)
If (And(CSTE, 8)) {
Return (0x1f)
}
Return(0x1d)
}
/* Query Device Graphics State */
Method(_DGS, 0)
{
If (And(NSTE, 4)) {
Return(1)
}
Return(0)
}
/* Device Set State */
Method(_DSS, 1)
{
/* If Parameter Arg0 is (1 << 31) | (1 << 30), the
* display switch was completed
*/
If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
Store (NSTE, CSTE)
}
}
}
Device(DD05)
{
/* Device Unique ID */
Method(_ADR, 0, Serialized)
{
If(LEqual(DID5, 0)) {
Return (5)
} Else {
Return (And(0xffff, DID5))
}
}
/* Device Current Status */
Method(_DCS, 0)
{
TRAP(1)
If (And(CSTE, 16)) {
Return (0x1f)
}
Return(0x1d)
}
/* Query Device Graphics State */
Method(_DGS, 0)
{
If (And(NSTE, 4)) {
Return(1)
}
Return(0)
}
/* Device Set State */
Method(_DSS, 1)
{
/* If Parameter Arg0 is (1 << 31) | (1 << 30), the
* display switch was completed
*/
If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
Store (NSTE, CSTE)
}
}
}
}

59
src/northbridge/intel/nehalem/acpi/nehalem.asl Normal file
View File

@ -0,0 +1,59 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include "../nehalem.h"
#include "hostbridge.asl"
/* PCI Device Resource Consumption */
Device (PDRC)
{
Name (_HID, EISAID("PNP0C02"))
Name (_UID, 1)
Name (PDRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA
Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000)
Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x04000000)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
#if CONFIG_CHROMEOS_RAMOOPS
Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START,
CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE)
#endif
/* Required for SandyBridge sighting 3715511 */
Memory32Fixed(ReadWrite, 0x20000000, 0x00200000)
Memory32Fixed(ReadWrite, 0x40000000, 0x00200000)
})
// Current Resource Settings
Method (_CRS, 0, Serialized)
{
Return(PDRS)
}
}
// Integrated graphics 0:2.0
#include "igd.asl"

7
src/northbridge/intel/nehalem/bootblock.c Normal file
View File

@ -0,0 +1,7 @@
#include <arch/io.h>
static void bootblock_northbridge_init(void)
{
pci_io_write_config32(PCI_DEV(0xff, 0x00, 1), 0x50, DEFAULT_PCIEXBAR | 1);
pci_io_write_config32(PCI_DEV(0xff, 0x00, 1), 0x54, 0);
}

42
src/northbridge/intel/nehalem/chip.h Normal file
View File

@ -0,0 +1,42 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2008 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/*
* Digital Port Hotplug Enable:
* 0x04 = Enabled, 2ms short pulse
* 0x05 = Enabled, 4.5ms short pulse
* 0x06 = Enabled, 6ms short pulse
* 0x07 = Enabled, 100ms short pulse
*/
struct northbridge_intel_nehalem_config {
u8 gpu_dp_b_hotplug; /* Digital Port B Hotplug Config */
u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */
u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */
u8 gpu_panel_port_select; /* 0=LVDS 1=DP_B 2=DP_C 3=DP_D */
u8 gpu_panel_power_cycle_delay; /* T4 time sequence */
u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */
u16 gpu_panel_power_down_delay; /* T3 time sequence */
u16 gpu_panel_power_backlight_on_delay; /* T5 time sequence */
u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */
u32 gpu_cpu_backlight; /* CPU Backlight PWM value */
u32 gpu_pch_backlight; /* PCH Backlight PWM value */
};

169
src/northbridge/intel/nehalem/early_init.c Normal file
View File

@ -0,0 +1,169 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2010 coresystems GmbH
* Copyright (C) 2011 Google Inc
* Copyright (C) 2013 Vladimir Serbinenko
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <stdint.h>
#include <stdlib.h>
#include <console/console.h>
#include <arch/io.h>
#include <device/pci_def.h>
#include <elog.h>
#include <cpu/x86/msr.h>
#include <cpu/intel/speedstep.h>
#include <cpu/intel/turbo.h>
#include <arch/cpu.h>
#include "nehalem.h"
static void nehalem_setup_bars(void)
{
/* Setting up Southbridge. In the northbridge code. */
printk(BIOS_DEBUG, "Setting up static southbridge registers...");
pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, DEFAULT_RCBA | 1);
pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
/* Enable ACPI BAR */
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80);
printk(BIOS_DEBUG, " done.\n");
printk(BIOS_DEBUG, "Disabling Watchdog reboot...");
/* No reset */
RCBA32(GCS) = RCBA32(GCS) | (1 << 5);
/* halt timer */
outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08);
/* halt timer */
outw(inw(DEFAULT_PMBASE | 0x60 | 0x06) | 2,
DEFAULT_PMBASE | 0x60 | 0x06);
printk(BIOS_DEBUG, " done.\n");
printk(BIOS_DEBUG, "Setting up static northbridge registers...");
/* Set up all hardcoded northbridge BARs */
pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1);
pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4,
(0LL + DEFAULT_EPBAR) >> 32);
pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1);
pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4,
(0LL + DEFAULT_MCHBAR) >> 32);
pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1);
pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4,
(0LL + DEFAULT_DMIBAR) >> 32);
/* Set C0000-FFFFF to access RAM on both reads and writes */
pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(0), 0x30);
pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(1), 0x33);
pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(2), 0x33);
pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(3), 0x33);
pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(4), 0x33);
pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(5), 0x33);
pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(6), 0x33);
#if CONFIG_ELOG_BOOT_COUNT
/* Increment Boot Counter for non-S3 resume */
if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&
((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3)
boot_count_increment();
#endif
printk(BIOS_DEBUG, " done.\n");
#if CONFIG_ELOG_BOOT_COUNT
/* Increment Boot Counter except when resuming from S3 */
if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&
((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3)
return;
boot_count_increment();
#endif
}
static void early_cpu_init (void)
{
msr_t m;
/* bit 0 = disable multicore,
bit 1 = disable quadcore,
bit 8 = disable hyperthreading. */
pci_write_config32(PCI_DEV(0xff, 0x00, 0), 0x80,
(pci_read_config32(PCI_DEV(0xff, 0x0, 0x0), 0x80) & 0xfffffefc) | 0x10000);
u8 reg8;
struct cpuid_result result;
result = cpuid_ext(0x6, 0x8b);
if (!(result.eax & 0x2)) {
m = rdmsr(MSR_FSB_CLOCK_VCC);
reg8 = ((m.lo & 0xff00) >> 8) + 1;
m = rdmsr (IA32_PERF_CTL);
m.lo = (m.lo & ~0xff) | reg8;
wrmsr(IA32_PERF_CTL, m);
m = rdmsr(MSR_IA32_MISC_ENABLES);
m.hi &= ~0x00000040;
m.lo |= 0x10000;
wrmsr(MSR_IA32_MISC_ENABLES, m);
}
m = rdmsr(MSR_FSB_CLOCK_VCC);
reg8 = ((m.lo & 0xff00) >> 8) + 1;
m = rdmsr (IA32_PERF_CTL);
m.lo = (m.lo & ~0xff) | reg8;
wrmsr(IA32_PERF_CTL, m);
m = rdmsr(MSR_IA32_MISC_ENABLES);
m.lo |= 0x10000;
wrmsr(MSR_IA32_MISC_ENABLES, m);
m = rdmsr(0x1f1);
m.lo |= 1;
wrmsr(0x1f1, m);
}
void nehalem_early_initialization(int chipset_type)
{
u32 capid0_a;
u8 reg8;
/* Device ID Override Enable should be done very early */
capid0_a = pci_read_config32(PCI_DEV(0, 0, 0), 0xe4);
if (capid0_a & (1 << 10)) {
reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf3);
reg8 &= ~7; /* Clear 2:0 */
if (chipset_type == NEHALEM_MOBILE)
reg8 |= 1; /* Set bit 0 */
pci_write_config8(PCI_DEV(0, 0, 0), 0xf3, reg8);
}
/* Setup all BARs required for early PCIe and raminit */
nehalem_setup_bars();
/* Device Enable */
pci_write_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN, 9 | 2);
early_cpu_init();
pci_write_config32(PCI_DEV(0, 0x16, 0), 0x10, DEFAULT_HECIBAR);
pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_COMMAND,
PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
}

1819
src/northbridge/intel/nehalem/fake_vbios.c Normal file
View File

File diff suppressed because it is too large Load Diff

56
src/northbridge/intel/nehalem/finalize.c Normal file
View File

@ -0,0 +1,56 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/io.h>
#include <stdlib.h>
#include "nehalem.h"
#define PCI_DEV_SNB PCI_DEV(0, 0, 0)
void intel_sandybridge_finalize_smm(void)
{
pcie_or_config16(PCI_DEV_SNB, 0x50, 1 << 0); /* GGC */
pcie_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0); /* DPR */
pcie_or_config32(PCI_DEV_SNB, 0x78, 1 << 10); /* ME */
pcie_or_config32(PCI_DEV_SNB, 0x90, 1 << 0); /* REMAPBASE */
pcie_or_config32(PCI_DEV_SNB, 0x98, 1 << 0); /* REMAPLIMIT */
pcie_or_config32(PCI_DEV_SNB, 0xa0, 1 << 0); /* TOM */
pcie_or_config32(PCI_DEV_SNB, 0xa8, 1 << 0); /* TOUUD */
pcie_or_config32(PCI_DEV_SNB, 0xb0, 1 << 0); /* BDSM */
pcie_or_config32(PCI_DEV_SNB, 0xb4, 1 << 0); /* BGSM */
pcie_or_config32(PCI_DEV_SNB, 0xb8, 1 << 0); /* TSEGMB */
pcie_or_config32(PCI_DEV_SNB, 0xbc, 1 << 0); /* TOLUD */
MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */
MCHBAR32_OR(0x5f00, 1 << 31); /* SA PM */
MCHBAR32_OR(0x6020, 1 << 0); /* UMA GFX */
MCHBAR32_OR(0x63fc, 1 << 0); /* VTDTRK */
MCHBAR32_OR(0x6800, 1 << 31);
MCHBAR32_OR(0x7000, 1 << 31);
MCHBAR32_OR(0x77fc, 1 << 0);
/* Memory Controller Lockdown */
MCHBAR8(0x50fc) = 0x8f;
/* Read+write the following */
MCHBAR32(0x6030) = MCHBAR32(0x6030);
MCHBAR32(0x6034) = MCHBAR32(0x6034);
MCHBAR32(0x6008) = MCHBAR32(0x6008);
}

748
src/northbridge/intel/nehalem/gma.c Normal file
View File

@ -0,0 +1,748 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Chromium OS Authors
* Copyright (C) 2013 Vladimir Serbinenko
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/io.h>
#include <console/console.h>
#include <delay.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <string.h>
#include <device/pci_ops.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include "chip.h"
#include "nehalem.h"
struct gt_powermeter {
u16 reg;
u32 value;
};
static const struct gt_powermeter snb_pm_gt1[] = {
{0xa200, 0xcc000000},
{0xa204, 0x07000040},
{0xa208, 0x0000fe00},
{0xa20c, 0x00000000},
{0xa210, 0x17000000},
{0xa214, 0x00000021},
{0xa218, 0x0817fe19},
{0xa21c, 0x00000000},
{0xa220, 0x00000000},
{0xa224, 0xcc000000},
{0xa228, 0x07000040},
{0xa22c, 0x0000fe00},
{0xa230, 0x00000000},
{0xa234, 0x17000000},
{0xa238, 0x00000021},
{0xa23c, 0x0817fe19},
{0xa240, 0x00000000},
{0xa244, 0x00000000},
{0xa248, 0x8000421e},
{0}
};
static const struct gt_powermeter snb_pm_gt2[] = {
{0xa200, 0x330000a6},
{0xa204, 0x402d0031},
{0xa208, 0x00165f83},
{0xa20c, 0xf1000000},
{0xa210, 0x00000000},
{0xa214, 0x00160016},
{0xa218, 0x002a002b},
{0xa21c, 0x00000000},
{0xa220, 0x00000000},
{0xa224, 0x330000a6},
{0xa228, 0x402d0031},
{0xa22c, 0x00165f83},
{0xa230, 0xf1000000},
{0xa234, 0x00000000},
{0xa238, 0x00160016},
{0xa23c, 0x002a002b},
{0xa240, 0x00000000},
{0xa244, 0x00000000},
{0xa248, 0x8000421e},
{0}
};
static const struct gt_powermeter ivb_pm_gt1[] = {
{0xa800, 0x00000000},
{0xa804, 0x00021c00},
{0xa808, 0x00000403},
{0xa80c, 0x02001700},
{0xa810, 0x05000200},
{0xa814, 0x00000000},
{0xa818, 0x00690500},
{0xa81c, 0x0000007f},
{0xa820, 0x01002501},
{0xa824, 0x00000300},
{0xa828, 0x01000331},
{0xa82c, 0x0000000c},
{0xa830, 0x00010016},
{0xa834, 0x01100101},
{0xa838, 0x00010103},
{0xa83c, 0x00041300},
{0xa840, 0x00000b30},
{0xa844, 0x00000000},
{0xa848, 0x7f000000},
{0xa84c, 0x05000008},
{0xa850, 0x00000001},
{0xa854, 0x00000004},
{0xa858, 0x00000007},
{0xa85c, 0x00000000},
{0xa860, 0x00010000},
{0xa248, 0x0000221e},
{0xa900, 0x00000000},
{0xa904, 0x00001c00},
{0xa908, 0x00000000},
{0xa90c, 0x06000000},
{0xa910, 0x09000200},
{0xa914, 0x00000000},
{0xa918, 0x00590000},
{0xa91c, 0x00000000},
{0xa920, 0x04002501},
{0xa924, 0x00000100},
{0xa928, 0x03000410},
{0xa92c, 0x00000000},
{0xa930, 0x00020000},
{0xa934, 0x02070106},
{0xa938, 0x00010100},
{0xa93c, 0x00401c00},
{0xa940, 0x00000000},
{0xa944, 0x00000000},
{0xa948, 0x10000e00},
{0xa94c, 0x02000004},
{0xa950, 0x00000001},
{0xa954, 0x00000004},
{0xa960, 0x00060000},
{0xaa3c, 0x00001c00},
{0xaa54, 0x00000004},
{0xaa60, 0x00060000},
{0}
};
static const struct gt_powermeter ivb_pm_gt2[] = {
{0xa800, 0x10000000},
{0xa804, 0x00033800},
{0xa808, 0x00000902},
{0xa80c, 0x0c002f00},
{0xa810, 0x12000400},
{0xa814, 0x00000000},
{0xa818, 0x00d20800},
{0xa81c, 0x00000002},
{0xa820, 0x03004b02},
{0xa824, 0x00000600},
{0xa828, 0x07000773},
{0xa82c, 0x00000000},
{0xa830, 0x00010032},
{0xa834, 0x1520040d},
{0xa838, 0x00020105},
{0xa83c, 0x00083700},
{0xa840, 0x0000151d},
{0xa844, 0x00000000},
{0xa848, 0x20001b00},
{0xa84c, 0x0a000010},
{0xa850, 0x00000000},
{0xa854, 0x00000008},
{0xa858, 0x00000008},
{0xa85c, 0x00000000},
{0xa860, 0x00020000},
{0xa248, 0x0000221e},
{0xa900, 0x00000000},
{0xa904, 0x00003500},
{0xa908, 0x00000000},
{0xa90c, 0x0c000000},
{0xa910, 0x12000500},
{0xa914, 0x00000000},
{0xa918, 0x00b20000},
{0xa91c, 0x00000000},
{0xa920, 0x08004b02},
{0xa924, 0x00000200},
{0xa928, 0x07000820},
{0xa92c, 0x00000000},
{0xa930, 0x00030000},
{0xa934, 0x050f020d},
{0xa938, 0x00020300},
{0xa93c, 0x00903900},
{0xa940, 0x00000000},
{0xa944, 0x00000000},
{0xa948, 0x20001b00},
{0xa94c, 0x0a000010},
{0xa950, 0x00000000},
{0xa954, 0x00000008},
{0xa960, 0x00110000},
{0xaa3c, 0x00003900},
{0xaa54, 0x00000008},
{0xaa60, 0x00110000},
{0}
};
static const struct gt_powermeter ivb_pm_gt2_17w[] = {
{0xa800, 0x20000000},
{0xa804, 0x000e3800},
{0xa808, 0x00000806},
{0xa80c, 0x0c002f00},
{0xa810, 0x0c000800},
{0xa814, 0x00000000},
{0xa818, 0x00d20d00},
{0xa81c, 0x000000ff},
{0xa820, 0x03004b02},
{0xa824, 0x00000600},
{0xa828, 0x07000773},
{0xa82c, 0x00000000},
{0xa830, 0x00020032},
{0xa834, 0x1520040d},
{0xa838, 0x00020105},
{0xa83c, 0x00083700},
{0xa840, 0x000016ff},
{0xa844, 0x00000000},
{0xa848, 0xff000000},
{0xa84c, 0x0a000010},
{0xa850, 0x00000002},
{0xa854, 0x00000008},
{0xa858, 0x0000000f},
{0xa85c, 0x00000000},
{0xa860, 0x00020000},
{0xa248, 0x0000221e},
{0xa900, 0x00000000},
{0xa904, 0x00003800},
{0xa908, 0x00000000},
{0xa90c, 0x0c000000},
{0xa910, 0x12000800},
{0xa914, 0x00000000},
{0xa918, 0x00b20000},
{0xa91c, 0x00000000},
{0xa920, 0x08004b02},
{0xa924, 0x00000300},
{0xa928, 0x01000820},
{0xa92c, 0x00000000},
{0xa930, 0x00030000},
{0xa934, 0x15150406},
{0xa938, 0x00020300},
{0xa93c, 0x00903900},
{0xa940, 0x00000000},
{0xa944, 0x00000000},
{0xa948, 0x20001b00},
{0xa94c, 0x0a000010},
{0xa950, 0x00000000},
{0xa954, 0x00000008},
{0xa960, 0x00110000},
{0xaa3c, 0x00003900},
{0xaa54, 0x00000008},
{0xaa60, 0x00110000},
{0}
};
static const struct gt_powermeter ivb_pm_gt2_35w[] = {
{0xa800, 0x00000000},
{0xa804, 0x00030400},
{0xa808, 0x00000806},
{0xa80c, 0x0c002f00},
{0xa810, 0x0c000300},
{0xa814, 0x00000000},
{0xa818, 0x00d20d00},
{0xa81c, 0x000000ff},
{0xa820, 0x03004b02},
{0xa824, 0x00000600},
{0xa828, 0x07000773},
{0xa82c, 0x00000000},
{0xa830, 0x00020032},
{0xa834, 0x1520040d},
{0xa838, 0x00020105},
{0xa83c, 0x00083700},
{0xa840, 0x000016ff},
{0xa844, 0x00000000},
{0xa848, 0xff000000},
{0xa84c, 0x0a000010},
{0xa850, 0x00000001},
{0xa854, 0x00000008},
{0xa858, 0x00000008},
{0xa85c, 0x00000000},
{0xa860, 0x00020000},
{0xa248, 0x0000221e},
{0xa900, 0x00000000},
{0xa904, 0x00003800},
{0xa908, 0x00000000},
{0xa90c, 0x0c000000},
{0xa910, 0x12000800},
{0xa914, 0x00000000},
{0xa918, 0x00b20000},
{0xa91c, 0x00000000},
{0xa920, 0x08004b02},
{0xa924, 0x00000300},
{0xa928, 0x01000820},
{0xa92c, 0x00000000},
{0xa930, 0x00030000},
{0xa934, 0x15150406},
{0xa938, 0x00020300},
{0xa93c, 0x00903900},
{0xa940, 0x00000000},
{0xa944, 0x00000000},
{0xa948, 0x20001b00},
{0xa94c, 0x0a000010},
{0xa950, 0x00000000},
{0xa954, 0x00000008},
{0xa960, 0x00110000},
{0xaa3c, 0x00003900},
{0xaa54, 0x00000008},
{0xaa60, 0x00110000},
{0}
};
/* some vga option roms are used for several chipsets but they only have one
* PCI ID in their header. If we encounter such an option rom, we need to do
* the mapping ourselfes
*/
u32 map_oprom_vendev(u32 vendev)
{
u32 new_vendev = vendev;
/* none curently. */
return new_vendev;
}
static struct resource *gtt_res = NULL;
static inline u32 gtt_read(u32 reg)
{
return read32(gtt_res->base + reg);
}
static inline void gtt_write(u32 reg, u32 data)
{
write32(gtt_res->base + reg, data);
}
static inline void gtt_write_powermeter(const struct gt_powermeter *pm)
{
for (; pm && pm->reg; pm++)
gtt_write(pm->reg, pm->value);
}
#define GTT_RETRY 1000
static int gtt_poll(u32 reg, u32 mask, u32 value)
{
unsigned try = GTT_RETRY;
u32 data;
while (try--) {
data = gtt_read(reg);
if ((data & mask) == value)
return 1;
udelay(10);
}
printk(BIOS_ERR, "GT init timeout\n");
return 0;
}
static void gma_pm_init_pre_vbios(struct device *dev)
{
u32 reg32;
printk(BIOS_DEBUG, "GT Power Management Init\n");
gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (!gtt_res || !gtt_res->base)
return;
if (bridge_silicon_revision() < IVB_STEP_C0) {
/* 1: Enable force wake */
gtt_write(0xa18c, 0x00000001);
gtt_poll(0x130090, (1 << 0), (1 << 0));
} else {
gtt_write(0xa180, 1 << 5);
gtt_write(0xa188, 0xffff0001);
gtt_poll(0x130040, (1 << 0), (1 << 0));
}
if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
/* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */
reg32 = gtt_read(0x42004);
reg32 |= (1 << 14) | (1 << 15);
gtt_write(0x42004, reg32);
}
if (bridge_silicon_revision() >= IVB_STEP_A0) {
/* Display Reset Acknowledge Settings */
reg32 = gtt_read(0x45010);
reg32 |= (1 << 1) | (1 << 0);
gtt_write(0x45010, reg32);
}
/* 2: Get GT SKU from GTT+0x911c[13] */
reg32 = gtt_read(0x911c);
if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
if (reg32 & (1 << 13)) {
printk(BIOS_DEBUG, "SNB GT1 Power Meter Weights\n");
gtt_write_powermeter(snb_pm_gt1);
} else {
printk(BIOS_DEBUG, "SNB GT2 Power Meter Weights\n");
gtt_write_powermeter(snb_pm_gt2);
}
} else {
u32 unit = MCHBAR32(0x5938) & 0xf;
if (reg32 & (1 << 13)) {
/* GT1 SKU */
printk(BIOS_DEBUG, "IVB GT1 Power Meter Weights\n");
gtt_write_powermeter(ivb_pm_gt1);
} else {
/* GT2 SKU */
u32 tdp = MCHBAR32(0x5930) & 0x7fff;
tdp /= (1 << unit);
if (tdp <= 17) {
/* <=17W ULV */
printk(BIOS_DEBUG, "IVB GT2 17W "
"Power Meter Weights\n");
gtt_write_powermeter(ivb_pm_gt2_17w);
} else if ((tdp >= 25) && (tdp <= 35)) {
/* 25W-35W */
printk(BIOS_DEBUG, "IVB GT2 25W-35W "
"Power Meter Weights\n");
gtt_write_powermeter(ivb_pm_gt2_35w);
} else {
/* All others */
printk(BIOS_DEBUG, "IVB GT2 35W "
"Power Meter Weights\n");
gtt_write_powermeter(ivb_pm_gt2_35w);
}
}
}
/* 3: Gear ratio map */
gtt_write(0xa004, 0x00000010);
/* 4: GFXPAUSE */
gtt_write(0xa000, 0x00070020);
/* 5: Dynamic EU trip control */
gtt_write(0xa080, 0x00000004);
/* 6: ECO bits */
reg32 = gtt_read(0xa180);
reg32 |= (1 << 26) | (1 << 31);
/* (bit 20=1 for SNB step D1+ / IVB A0+) */
if (bridge_silicon_revision() >= SNB_STEP_D1)
reg32 |= (1 << 20);
gtt_write(0xa180, reg32);
/* 6a: for SnB step D2+ only */
if (((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) &&
(bridge_silicon_revision() >= SNB_STEP_D2)) {
reg32 = gtt_read(0x9400);
reg32 |= (1 << 7);
gtt_write(0x9400, reg32);
reg32 = gtt_read(0x941c);
reg32 &= 0xf;
reg32 |= (1 << 1);
gtt_write(0x941c, reg32);
gtt_poll(0x941c, (1 << 1), (0 << 1));
}
if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
reg32 = gtt_read(0x907c);
reg32 |= (1 << 16);
gtt_write(0x907c, reg32);
/* 6b: Clocking reset controls */
gtt_write(0x9424, 0x00000001);
} else {
/* 6b: Clocking reset controls */
gtt_write(0x9424, 0x00000000);
}
/* 7 */
if (gtt_poll(0x138124, (1 << 31), (0 << 31))) {
gtt_write(0x138128, 0x00000029); /* Mailbox Data */
gtt_write(0x138124, 0x80000004); /* Mailbox Cmd for RC6 VID */
if (gtt_poll(0x138124, (1 << 31), (0 << 31)))
gtt_write(0x138124, 0x8000000a);
gtt_poll(0x138124, (1 << 31), (0 << 31));
}
/* 8 */
gtt_write(0xa090, 0x00000000); /* RC Control */
gtt_write(0xa098, 0x03e80000); /* RC1e Wake Rate Limit */
gtt_write(0xa09c, 0x0028001e); /* RC6/6p Wake Rate Limit */
gtt_write(0xa0a0, 0x0000001e); /* RC6pp Wake Rate Limit */
gtt_write(0xa0a8, 0x0001e848); /* RC Evaluation Interval */
gtt_write(0xa0ac, 0x00000019); /* RC Idle Hysteresis */
/* 9 */
gtt_write(0x2054, 0x0000000a); /* Render Idle Max Count */
gtt_write(0x12054, 0x0000000a); /* Video Idle Max Count */
gtt_write(0x22054, 0x0000000a); /* Blitter Idle Max Count */
/* 10 */
gtt_write(0xa0b0, 0x00000000); /* Unblock Ack to Busy */
gtt_write(0xa0b4, 0x000003e8); /* RC1e Threshold */
gtt_write(0xa0b8, 0x0000c350); /* RC6 Threshold */
gtt_write(0xa0bc, 0x000186a0); /* RC6p Threshold */
gtt_write(0xa0c0, 0x0000fa00); /* RC6pp Threshold */
/* 11 */
gtt_write(0xa010, 0x000f4240); /* RP Down Timeout */
gtt_write(0xa014, 0x12060000); /* RP Interrupt Limits */
gtt_write(0xa02c, 0x00015f90); /* RP Up Threshold */
gtt_write(0xa030, 0x000186a0); /* RP Down Threshold */
gtt_write(0xa068, 0x000186a0); /* RP Up EI */
gtt_write(0xa06c, 0x000493e0); /* RP Down EI */
gtt_write(0xa070, 0x0000000a); /* RP Idle Hysteresis */
/* 11a: Enable Render Standby (RC6) */
if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
/*
* IvyBridge should also support DeepRenderStandby.
*
* Unfortunately it does not work reliably on all SKUs so
* disable it here and it can be enabled by the kernel.
*/
gtt_write(0xa090, 0x88040000); /* HW RC Control */
} else {
gtt_write(0xa090, 0x88040000); /* HW RC Control */
}
/* 12: Normal Frequency Request */
/* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 (8 bits!? use 7) */
reg32 = MCHBAR32(0x5998);
reg32 >>= 16;
reg32 &= 0xef;
reg32 <<= 25;
gtt_write(0xa008, reg32);
/* 13: RP Control */
gtt_write(0xa024, 0x00000592);
/* 14: Enable PM Interrupts */
gtt_write(0x4402c, 0x03000076);
/* Clear 0x6c024 [8:6] */
reg32 = gtt_read(0x6c024);
reg32 &= ~0x000001c0;
gtt_write(0x6c024, reg32);
}
#include <pc80/vga.h>
#include <pc80/vga_io.h>
static void fake_vbios(void)
{
#include "fake_vbios.c"
}
static void gma_pm_init_post_vbios(struct device *dev)
{
struct northbridge_intel_nehalem_config *conf = dev->chip_info;
u32 reg32;
printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n");
/* 15: Deassert Force Wake */
if (bridge_silicon_revision() < IVB_STEP_C0) {
gtt_write(0xa18c, gtt_read(0xa18c) & ~1);
gtt_poll(0x130090, (1 << 0), (0 << 0));
} else {
gtt_write(0xa188, 0x1fffe);
if (gtt_poll(0x130040, (1 << 0), (0 << 0)))
gtt_write(0xa188, gtt_read(0xa188) | 1);
}
/* 16: SW RC Control */
gtt_write(0xa094, 0x00060000);
/* Setup Digital Port Hotplug */
reg32 = gtt_read(0xc4030);
if (!reg32) {
reg32 = (conf->gpu_dp_b_hotplug & 0x7) << 2;
reg32 |= (conf->gpu_dp_c_hotplug & 0x7) << 10;
reg32 |= (conf->gpu_dp_d_hotplug & 0x7) << 18;
gtt_write(0xc4030, reg32);
}
/* Setup Panel Power On Delays */
reg32 = gtt_read(0xc7208);
if (!reg32) {
reg32 = (conf->gpu_panel_port_select & 0x3) << 30;
reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16;
reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff);
gtt_write(0xc7208, reg32);
}
/* Setup Panel Power Off Delays */
reg32 = gtt_read(0xc720c);
if (!reg32) {
reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16;
reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff);
gtt_write(0xc720c, reg32);
}
/* Setup Panel Power Cycle Delay */
if (conf->gpu_panel_power_cycle_delay) {
reg32 = gtt_read(0xc7210);
reg32 &= ~0xff;
reg32 |= conf->gpu_panel_power_cycle_delay & 0xff;
gtt_write(0xc7210, reg32);
}
/* Enable Backlight if needed */
if (conf->gpu_cpu_backlight) {
gtt_write(0x48250, (1 << 31));
gtt_write(0x48254, conf->gpu_cpu_backlight);
}
if (conf->gpu_pch_backlight) {
gtt_write(0xc8250, (1 << 31));
gtt_write(0xc8254, conf->gpu_pch_backlight);
}
}
static void gma_func0_init(struct device *dev)
{
u32 reg32;
/* IGD needs to be Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
pci_write_config32(dev, PCI_COMMAND, reg32);
/* Init graphics power management */
gma_pm_init_pre_vbios(dev);
#if !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
/* PCI Init, will run VBIOS */
pci_dev_init(dev);
#else
printk(BIOS_SPEW, "Initializing VGA without OPROM.\n");
#endif
fake_vbios();
/* Linux relies on VBT for panel info. */
if (read16(0xc0000) != 0xaa55) {
optionrom_header_t *oh = (void *)0xc0000;
optionrom_pcir_t *pcir;
int sz;
memset(oh->reserved, 0, 8192);
sz = (0x80 + sizeof(fake_vbt) + 511) / 512;
oh->signature = 0xaa55;
oh->size = sz;
oh->pcir_offset = 0x40;
oh->vbt_offset = 0x80;
pcir = (void *)0xc0040;
pcir->signature = 0x52494350; // PCIR
pcir->vendor = dev->vendor;
pcir->device = dev->device;
pcir->length = sizeof(*pcir);
pcir->revision = dev->class;
pcir->classcode[0] = dev->class >> 8;
pcir->classcode[1] = dev->class >> 16;
pcir->classcode[2] = dev->class >> 24;
pcir->imagelength = sz;
pcir->indicator = 0x80;
memcpy((void *)0xc0080, fake_vbt, sizeof(fake_vbt));
}
/* Post VBIOS init */
gma_pm_init_post_vbios(dev);
#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
/* This should probably run before post VBIOS init. */
u32 iobase, mmiobase, physbase, graphics_base;
iobase = dev->resource_list[2].base;
mmiobase = dev->resource_list[0].base;
physbase = pci_read_config32(dev, 0x5c) & ~0xf;
graphics_base = dev->resource_list[1].base;
int i915lightup(u32 physbase, u32 iobase, u32 mmiobase, u32 gfx);
i915lightup(physbase, iobase, mmiobase, graphics_base);
#endif
}
static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor &
0xffff));
}
}
static void gma_read_resources(struct device *dev)
{
pci_dev_read_resources(dev);
struct resource *res;
/* Set the graphics memory to write combining. */
res = find_resource(dev, PCI_BASE_ADDRESS_2);
if (res == NULL) {
printk(BIOS_DEBUG, "gma: memory resource not found.\n");
return;
}
res->flags |= IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_ASSIGNED;
pci_write_config32(dev, PCI_BASE_ADDRESS_2,
0xd0000001);
pci_write_config32(dev, PCI_BASE_ADDRESS_2 + 4,
0);
#if CONFIG_MARK_GRAPHICS_MEM_WRCOMB
res->flags |= IORESOURCE_WRCOMB;
#endif
res->base = (resource_t) 0xd0000000;
res->size = (resource_t) 0x10000000;
}
static struct pci_operations gma_pci_ops = {
.set_subsystem = gma_set_subsystem,
};
static struct device_operations gma_func0_ops = {
.read_resources = gma_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = gma_func0_init,
.scan_bus = 0,
.enable = 0,
.ops_pci = &gma_pci_ops,
};
static const unsigned short pci_device_ids[] =
{ 0x0046, 0x0102, 0x0106, 0x010a, 0x0112,
0x0116, 0x0122, 0x0126, 0x0156,
0x0166,
0
};
static const struct pci_driver gma __pci_driver = {
.ops = &gma_func0_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.devices = pci_device_ids,
};

173
src/northbridge/intel/nehalem/gma.h Normal file
View File

@ -0,0 +1,173 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Chromium OS Authors
* Copyright (C) 2013 Vladimir Serbinenko
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __NORTHBRIDGE_INTEL_NEHALEM_GMA_H__
#define __NORTHBRIDGE_INTEL_NEHALEM_GMA_H__ 1
/* mailbox 0: header */
typedef struct {
u8 signature[16];
u32 size;
u32 version;
u8 sbios_version[32];
u8 vbios_version[16];
u8 driver_version[16];
u32 mailboxes;
u8 reserved[164];
} __attribute__((packed)) opregion_header_t;
#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem"
#define IGD_OPREGION_VERSION 2
#define IGD_MBOX1 (1 << 0)
#define IGD_MBOX2 (1 << 1)
#define IGD_MBOX3 (1 << 2)
#define IGD_MBOX4 (1 << 3)
#define IGD_MBOX5 (1 << 4)
#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \
IGD_MBOX4 | IGD_MBOX5)
#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4)
#define SBIOS_VERSION_SIZE 32
/* mailbox 1: public acpi methods */
typedef struct {
u32 drdy;
u32 csts;
u32 cevt;
u8 reserved1[20];
u32 didl[8];
u32 cpdl[8];
u32 cadl[8];
u32 nadl[8];
u32 aslp;
u32 tidx;
u32 chpd;
u32 clid;
u32 cdck;
u32 sxsw;
u32 evts;
u32 cnot;
u32 nrdy;
u8 reserved2[60];
} __attribute__((packed)) opregion_mailbox1_t;
/* mailbox 2: software sci interface */
typedef struct {
u32 scic;
u32 parm;
u32 dslp;
u8 reserved[244];
} __attribute__((packed)) opregion_mailbox2_t;
/* mailbox 3: power conservation */
typedef struct {
u32 ardy;
u32 aslc;
u32 tche;
u32 alsi;
u32 bclp;
u32 pfit;
u32 cblv;
u16 bclm[20];
u32 cpfm;
u32 epfm;
u8 plut[74];
u32 pfmb;
u32 ccdv;
u32 pcft;
u8 reserved[94];
} __attribute__((packed)) opregion_mailbox3_t;
#define IGD_BACKLIGHT_BRIGHTNESS 0xff
#define IGD_INITIAL_BRIGHTNESS 0x64
#define IGD_FIELD_VALID (1 << 31)
#define IGD_WORD_FIELD_VALID (1 << 15)
#define IGD_PFIT_STRETCH 6
/* mailbox 4: vbt */
typedef struct {
u8 gvd1[7168];
} __attribute__((packed)) opregion_vbt_t;
/* IGD OpRegion */
typedef struct {
opregion_header_t header;
opregion_mailbox1_t mailbox1;
opregion_mailbox2_t mailbox2;
opregion_mailbox3_t mailbox3;
opregion_vbt_t vbt;
} __attribute__((packed)) igd_opregion_t;
/* Intel Video BIOS (Option ROM) */
typedef struct {
u16 signature;
u8 size;
u8 reserved[21];
u16 pcir_offset;
u16 vbt_offset;
} __attribute__((packed)) optionrom_header_t;
#define OPROM_SIGNATURE 0xaa55
typedef struct {
u32 signature;
u16 vendor;
u16 device;
u16 reserved1;
u16 length;
u8 revision;
u8 classcode[3];
u16 imagelength;
u16 coderevision;
u8 codetype;
u8 indicator;
u16 reserved2;
} __attribute__((packed)) optionrom_pcir_t;
typedef struct {
u8 hdr_signature[20];
u16 hdr_version;
u16 hdr_size;
u16 hdr_vbt_size;
u8 hdr_vbt_checksum;
u8 hdr_reserved;
u32 hdr_vbt_datablock;
u32 hdr_aim[4];
u8 datahdr_signature[16];
u16 datahdr_version;
u16 datahdr_size;
u16 datahdr_datablocksize;
u8 coreblock_id;
u16 coreblock_size;
u16 coreblock_biossize;
u8 coreblock_biostype;
u8 coreblock_releasestatus;
u8 coreblock_hwsupported;
u8 coreblock_integratedhw;
u8 coreblock_biosbuild[4];
u8 coreblock_biossignon[155];
} __attribute__((packed)) optionrom_vbt_t;
#define VBT_SIGNATURE 0x54425624
#endif

629
src/northbridge/intel/nehalem/nehalem.h Normal file
View File

@ -0,0 +1,629 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2008 coresystems GmbH
* Copyright (C) 2011 Google Inc.
* Copyright (C) 2013 Vladimir Serbinenko
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__
#define __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__ 1
#ifndef __ASSEMBLER__
#include <stdint.h>
extern unsigned char fake_vbt[4096];
typedef enum {
FSB_CLOCK_1067MHz = 0,
FSB_CLOCK_800MHz = 1,
FSB_CLOCK_667MHz = 2,
} fsb_clock_t;
typedef enum { /* Steppings below B1 were pre-production,
conversion stepping A1 is... ?
We'll support B1, B2, B3, and conversion stepping A1. */
STEPPING_A0 = 0,
STEPPING_A1 = 1,
STEPPING_A2 = 2,
STEPPING_A3 = 3,
STEPPING_B0 = 4,
STEPPING_B1 = 5,
STEPPING_B2 = 6,
STEPPING_B3 = 7,
STEPPING_CONVERSION_A1 = 9,
} stepping_t;
typedef enum {
GMCH_GM45 = 0,
GMCH_GM47,
GMCH_GM49,
GMCH_GE45,
GMCH_GL40,
GMCH_GL43,
GMCH_GS40,
GMCH_GS45,
GMCH_PM45,
GMCH_UNKNOWN
} gmch_gfx_t;
typedef enum {
MEM_CLOCK_533MHz = 0,
MEM_CLOCK_400MHz = 1,
MEM_CLOCK_333MHz = 2,
MEM_CLOCK_1067MT = 0,
MEM_CLOCK_800MT = 1,
MEM_CLOCK_667MT = 2,
} mem_clock_t;
typedef enum {
DDR1 = 1,
DDR2 = 2,
DDR3 = 3,
} ddr_t;
typedef enum {
CHANNEL_MODE_SINGLE,
CHANNEL_MODE_DUAL_ASYNC,
CHANNEL_MODE_DUAL_INTERLEAVED,
} channel_mode_t;
typedef enum { /* as in DDR3 spd */
CHIP_WIDTH_x4 = 0,
CHIP_WIDTH_x8 = 1,
CHIP_WIDTH_x16 = 2,
CHIP_WIDTH_x32 = 3,
} chip_width_t;
typedef enum { /* as in DDR3 spd */
CHIP_CAP_256M = 0,
CHIP_CAP_512M = 1,
CHIP_CAP_1G = 2,
CHIP_CAP_2G = 3,
CHIP_CAP_4G = 4,
CHIP_CAP_8G = 5,
CHIP_CAP_16G = 6,
} chip_capacity_t;
typedef struct {
unsigned int CAS;
fsb_clock_t fsb_clock;
mem_clock_t mem_clock;
channel_mode_t channel_mode;
unsigned int tRAS;
unsigned int tRP;
unsigned int tRCD;
unsigned int tRFC;
unsigned int tWR;
unsigned int tRD;
unsigned int tRRD;
unsigned int tFAW;
unsigned int tWL;
} timings_t;
typedef struct {
unsigned int card_type; /* 0x0: unpopulated,
0xa - 0xf: raw card type A - F */
chip_width_t chip_width;
chip_capacity_t chip_capacity;
unsigned int page_size; /* of whole DIMM in Bytes (4096 or 8192) */
unsigned int banks;
unsigned int ranks;
unsigned int rank_capacity_mb; /* per rank in Mega Bytes */
} dimminfo_t;
/* The setup is one DIMM per channel, so there's no need to find a
common timing setup between multiple chips (but chip and controller
still need to be coordinated */
typedef struct {
stepping_t stepping;
int txt_enabled;
int cores;
gmch_gfx_t gfx_type;
int gs45_low_power_mode; /* low power mode of GMCH_GS45 */
int max_ddr2_mhz;
int max_ddr3_mt;
fsb_clock_t max_fsb;
int max_fsb_mhz;
int max_render_mhz;
int spd_type;
timings_t selected_timings;
dimminfo_t dimms[2];
} sysinfo_t;
#define TOTAL_CHANNELS 2
#define CHANNEL_IS_POPULATED(dimms, idx) (dimms[idx].card_type != 0)
#define CHANNEL_IS_CARDF(dimms, idx) (dimms[idx].card_type == 0xf)
#define IF_CHANNEL_POPULATED(dimms, idx) if (dimms[idx].card_type != 0)
#define FOR_EACH_CHANNEL(idx) \
for (idx = 0; idx < TOTAL_CHANNELS; ++idx)
#define FOR_EACH_POPULATED_CHANNEL(dimms, idx) \
FOR_EACH_CHANNEL(idx) IF_CHANNEL_POPULATED(dimms, idx)
#define RANKS_PER_CHANNEL 4 /* Only two may be populated */
#define IF_RANK_POPULATED(dimms, ch, r) \
if (dimms[ch].card_type && ((r) < dimms[ch].ranks))
#define FOR_EACH_RANK_IN_CHANNEL(r) \
for (r = 0; r < RANKS_PER_CHANNEL; ++r)
#define FOR_EACH_POPULATED_RANK_IN_CHANNEL(dimms, ch, r) \
FOR_EACH_RANK_IN_CHANNEL(r) IF_RANK_POPULATED(dimms, ch, r)
#define FOR_EACH_RANK(ch, r) \
FOR_EACH_CHANNEL(ch) FOR_EACH_RANK_IN_CHANNEL(r)
#define FOR_EACH_POPULATED_RANK(dimms, ch, r) \
FOR_EACH_RANK(ch, r) IF_RANK_POPULATED(dimms, ch, r)
#define DDR3_MAX_CAS 18
enum {
VCO_2666 = 4,
VCO_3200 = 0,
VCO_4000 = 1,
VCO_5333 = 2,
};
#endif
/* Offsets of read/write training results in CMOS.
They will be restored upon S3 resumes. */
#define CMOS_READ_TRAINING 0x80 /* 16 bytes */
#define CMOS_WRITE_TRAINING 0x90 /* 16 bytes
(could be reduced to 10 bytes) */
#define DEFAULT_HECIBAR 0xfed17000
/* 4 KB per PCIe device */
#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS
#define IOMMU_BASE1 0xfed90000
#define IOMMU_BASE2 0xfed91000
#define IOMMU_BASE3 0xfed92000
#define IOMMU_BASE4 0xfed93000
/*
* D0:F0
*/
#define D0F0_EPBAR_LO 0x40
#define D0F0_EPBAR_HI 0x44
#define D0F0_MCHBAR_LO 0x48
#define D0F0_MCHBAR_HI 0x4c
#define D0F0_GGC 0x52
#define D0F0_DEVEN 0x54
#define DEVEN_PEG60 (1 << 13)
#define DEVEN_IGD (1 << 4)
#define DEVEN_PEG10 (1 << 3)
#define DEVEN_PEG11 (1 << 2)
#define DEVEN_PEG12 (1 << 1)
#define DEVEN_HOST (1 << 0)
#define D0F0_PCIEXBAR_LO 0x60
#define D0F0_PCIEXBAR_HI 0x64
#define D0F0_DMIBAR_LO 0x68
#define D0F0_DMIBAR_HI 0x6c
#define D0F0_PMBASE 0x78
#define QPD0F1_PAM(x) (0x40+(x)) /* 0-6*/
#define D0F0_REMAPBASE 0x98
#define D0F0_REMAPLIMIT 0x9a
#define D0F0_SMRAM 0x9d
#define D0F0_ESMRAMC 0x9e
#define D0F0_TOM 0xa0
#define D0F0_TOUUD 0xa2
#define D0F0_IGD_BASE 0xa4
#define D0F0_GTT_BASE 0xa8
#define D0F0_TOLUD 0xb0
#define D0F0_SKPD 0xdc /* Scratchpad Data */
#define SKPAD_ACPI_S3_MAGIC 0xcafed00d
#define SKPAD_NORMAL_BOOT_MAGIC 0xcafebabe
#define D0F0_CAPID0 0xe0
#define TSEG 0xac /* TSEG base */
/*
* D1:F0 PEG
*/
#define PEG_CAP 0xa2
#define SLOTCAP 0xb4
#define PEGLC 0xec
#define D1F0_VCCAP 0x104
#define D1F0_VC0RCTL 0x114
/*
* Graphics frequencies
*/
#define GCFGC_PCIDEV PCI_DEV(0, 2, 0)
#define GCFGC_OFFSET 0xf0
#define GCFGC_CR_SHIFT 0
#define GCFGC_CR_MASK (0xf << GCFGC_CR_SHIFT)
#define GCFGC_CS_SHIFT 8
#define GCFGC_CS_MASK (0xf << GCFGC_CS_SHIFT)
#define GCFGC_CD_SHIFT 12
#define GCFGC_CD_MASK (0x1 << GCFGC_CD_SHIFT)
#define GCFGC_UPDATE_SHIFT 5
#define GCFGC_UPDATE (0x1 << GCFGC_UPDATE_SHIFT)
/*
* MCHBAR
*/
#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x))
#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x))
#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x))
#define PMSTS_MCHBAR 0x0f14 /* Self refresh channel status */
#define PMSTS_WARM_RESET (1 << 1)
#define PMSTS_BOTH_SELFREFRESH (1 << 0)
#define CLKCFG_MCHBAR 0x0c00
#define CLKCFG_FSBCLK_SHIFT 0
#define CLKCFG_FSBCLK_MASK (7 << CLKCFG_FSBCLK_SHIFT)
#define CLKCFG_MEMCLK_SHIFT 4
#define CLKCFG_MEMCLK_MASK (7 << CLKCFG_MEMCLK_SHIFT)
#define CLKCFG_UPDATE (1 << 12)
#define SSKPD_MCHBAR 0x0c1c
#define SSKPD_CLK_SHIFT 0
#define SSKPD_CLK_MASK (7 << SSKPD_CLK_SHIFT)
#define DCC_MCHBAR 0x200
#define DCC_NO_CHANXOR (1 << 10)
#define DCC_INTERLEAVED (1 << 1)
#define DCC_CMD_SHIFT 16
#define DCC_CMD_MASK (7 << DCC_CMD_SHIFT)
#define DCC_CMD_NOP (1 << DCC_CMD_SHIFT)
/* For mode register mr0: */
#define DCC_SET_MREG (3 << DCC_CMD_SHIFT)
/* For extended mode registers mr1 to mr3: */
#define DCC_SET_EREG (4 << DCC_CMD_SHIFT)
#define DCC_SET_EREG_SHIFT 21
#define DCC_SET_EREG_MASK (DCC_CMD_MASK | (3 << DCC_SET_EREG_SHIFT))
#define DCC_SET_EREGx(x) ((DCC_SET_EREG | \
((x - 1) << DCC_SET_EREG_SHIFT)) & \
DCC_SET_EREG_MASK)
/* Per channel DRAM Row Attribute registers (32-bit) */
#define CxDRA_MCHBAR(x) (0x1208 + (x * 0x0100))
#define CxDRA_PAGESIZE_SHIFT(r) (r * 4) /* Per rank r */
#define CxDRA_PAGESIZE_MASKr(r) (0x7 << CxDRA_PAGESIZE_SHIFT(r))
#define CxDRA_PAGESIZE_MASK 0x0000ffff
#define CxDRA_PAGESIZE(r, p) /* for log2(dimm page size in bytes) p */ \
(((p - 10) << CxDRA_PAGESIZE_SHIFT(r)) & CxDRA_PAGESIZE_MASKr(r))
#define CxDRA_BANKS_SHIFT(r) ((r * 3) + 16)
#define CxDRA_BANKS_MASKr(r) (0x3 << CxDRA_BANKS_SHIFT(r))
#define CxDRA_BANKS_MASK 0x07ff0000
#define CxDRA_BANKS(r, b) /* for number of banks b */ \
((b << (CxDRA_BANKS_SHIFT(r) - 3)) & CxDRA_BANKS_MASKr(r))
/*
* Per channel DRAM Row Boundary registers (32-bit)
* Every two ranks share one register and must be programmed at the same time.
* All registers (4 ranks per channel) have to be set.
*/
#define CxDRBy_MCHBAR(x, r) (0x1200 + (x * 0x0100) + ((r/2) * 4))
#define CxDRBy_BOUND_SHIFT(r) ((r % 2) * 16)
#define CxDRBy_BOUND_MASK(r) (0x1fc << CxDRBy_BOUND_SHIFT(r))
#define CxDRBy_BOUND_MB(r, b) /* for boundary in MB b */ \
(((b >> 5) << CxDRBy_BOUND_SHIFT(r)) & CxDRBy_BOUND_MASK(r))
#define CxDRC0_MCHBAR(x) (0x1230 + (x * 0x0100))
#define CxDRC0_RANKEN0 (1 << 24) /* Rank Enable */
#define CxDRC0_RANKEN1 (1 << 25)
#define CxDRC0_RANKEN2 (1 << 26)
#define CxDRC0_RANKEN3 (1 << 27)
#define CxDRC0_RANKEN(r) (1 << (24 + r))
#define CxDRC0_RANKEN_MASK (0xf << 24)
#define CxDRC0_RMS_SHIFT 8 /* Refresh Mode Select */
#define CxDRC0_RMS_MASK (7 << CxDRC0_RMS_SHIFT)
#define CxDRC0_RMS_78US (2 << CxDRC0_RMS_SHIFT)
#define CxDRC0_RMS_39US (3 << CxDRC0_RMS_SHIFT)
#define CxDRC1_MCHBAR(x) (0x1234 + (x * 0x0100))
#define CxDRC1_SSDS_SHIFT 24
#define CxDRC1_SSDS_MASK (0xff << CxDRC1_SSDS_SHIFT)
#define CxDRC1_DS (0x91 << CxDRC1_SSDS_SHIFT)
#define CxDRC1_SS (0xb1 << CxDRC1_SSDS_SHIFT)
#define CxDRC1_NOTPOP(r) (1 << (16 + r)) /* Write 1 for Not Populated */
#define CxDRC1_NOTPOP_MASK (0xf << 16)
#define CxDRC1_MUSTWR (3 << 11)
#define CxDRC2_MCHBAR(x) (0x1238 + (x * 0x0100))
#define CxDRC2_NOTPOP(r) (1 << (24 + r)) /* Write 1 for Not Populated */
#define CxDRC2_NOTPOP_MASK (0xf << 24)
#define CxDRC2_MUSTWR (1 << 12)
#define CxDRC2_CLK1067MT (1 << 0)
/* DRAM Timing registers (32-bit each) */
#define CxDRT0_MCHBAR(x) (0x1210 + (x * 0x0100))
#define CxDRT0_BtB_WtP_SHIFT 26
#define CxDRT0_BtB_WtP_MASK (0x1f << CxDRT0_BtB_WtP_SHIFT)
#define CxDRT0_BtB_WtR_SHIFT 20
#define CxDRT0_BtB_WtR_MASK (0x1f << CxDRT0_BtB_WtR_SHIFT)
#define CxDRT1_MCHBAR(x) (0x1214 + (x * 0x0100))
#define CxDRT2_MCHBAR(x) (0x1218 + (x * 0x0100))
#define CxDRT3_MCHBAR(x) (0x121c + (x * 0x0100))
#define CxDRT4_MCHBAR(x) (0x1220 + (x * 0x0100))
#define CxDRT5_MCHBAR(x) (0x1224 + (x * 0x0100))
#define CxDRT6_MCHBAR(x) (0x1228 + (x * 0x0100))
/* Clock disable registers (32-bit each) */
#define CxDCLKDIS_MCHBAR(x) (0x120c + (x * 0x0100))
#define CxDCLKDIS_MASK 3
#define CxDCLKDIS_ENABLE 3 /* Always enable both clock pairs. */
/* On-Die-Termination registers (2x 32-bit per channel) */
#define CxODT_HIGH(x) (0x124c + (x * 0x0100))
#define CxODT_LOW(x) (0x1248 + (x * 0x0100))
/* Write Training registers. */
#define CxWRTy_MCHBAR(ch, s) (0x1470 + (ch * 0x0100) + ((3 - s) * 4))
#define CxGTEW(x) (0x1270+(x*0x100))
#define CxGTC(x) (0x1274+(x*0x100))
#define CxDTPEW(x) (0x1278+(x*0x100))
#define CxDTAEW(x) (0x1280+(x*0x100))
#define CxDTC(x) (0x1288+(x*0x100))
/*
* DMIBAR
*/
#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x))
#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x))
#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x))
#define DMIVC0RCTL 0x14
#define DMIESD 0x44
/*
* EPBAR
*/
#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x))
#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x))
#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x))
#ifndef __ASSEMBLER__
void gm45_early_init(void);
void gm45_early_reset(void);
void enter_raminit_or_reset(void);
void get_gmch_info(sysinfo_t *);
void raminit_thermal(const sysinfo_t *);
void init_igd(const sysinfo_t *, int no_igd, int no_peg);
void init_pm(const sysinfo_t *);
int raminit_read_vco_index(void);
u32 raminit_get_rank_addr(unsigned int channel, unsigned int rank);
void raminit_rcomp_calibration(stepping_t stepping);
void raminit_reset_readwrite_pointers(void);
void raminit_receive_enable_calibration(const timings_t *, const dimminfo_t *);
void raminit_write_training(const mem_clock_t, const dimminfo_t *, int s3resume);
void raminit_read_training(const dimminfo_t *, int s3resume);
void gm45_late_init(stepping_t);
u32 decode_igd_memory_size(u32 gms);
u32 decode_igd_gtt_size(u32 gsm);
void init_iommu(void);
#endif
/* Chipset types */
#define NEHALEM_MOBILE 0
#define NEHALEM_DESKTOP 1
#define NEHALEM_SERVER 2
/* Device ID for SandyBridge and IvyBridge */
#define BASE_REV_SNB 0x00
#define BASE_REV_IVB 0x50
#define BASE_REV_MASK 0x50
/* SandyBridge CPU stepping */
#define SNB_STEP_D0 (BASE_REV_SNB + 5) /* Also J0 */
#define SNB_STEP_D1 (BASE_REV_SNB + 6)
#define SNB_STEP_D2 (BASE_REV_SNB + 7) /* Also J1/Q0 */
/* IvyBridge CPU stepping */
#define IVB_STEP_A0 (BASE_REV_IVB + 0)
#define IVB_STEP_B0 (BASE_REV_IVB + 2)
#define IVB_STEP_C0 (BASE_REV_IVB + 4)
#define IVB_STEP_K0 (BASE_REV_IVB + 5)
#define IVB_STEP_D0 (BASE_REV_IVB + 6)
/* Intel Enhanced Debug region must be 4MB */
#define IED_SIZE 0x400000
/* Northbridge BARs */
#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */
#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */
#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */
#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
#define DEFAULT_RCBABASE 0xfed1c000
#define QUICKPATH_BUS 0xff
#include <southbridge/intel/ibexpeak/pch.h>
/* Everything below this line is ignored in the DSDT */
#ifndef __ACPI__
/* Device 0:0.0 PCI configuration space (Host Bridge) */
#define EPBAR 0x40
#define MCHBAR 0x48
#define PCIEXBAR 0x60
#define DMIBAR 0x68
#define X60BAR 0x60
#define LAC 0x87 /* Legacy Access Control */
#define SMRAM 0x88 /* System Management RAM Control */
#define D_OPEN (1 << 6)
#define D_CLS (1 << 5)
#define D_LCK (1 << 4)
#define G_SMRAME (1 << 3)
#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
#define SKPAD 0xdc /* Scratchpad Data */
/* Device 0:1.0 PCI configuration space (PCI Express) */
#define BCTRL1 0x3e /* 16bit */
/* Device 0:2.0 PCI configuration space (Graphics Device) */
#define MSAC 0x62 /* Multi Size Aperture Control */
#define SWSCI 0xe8 /* SWSCI enable */
#define ASLS 0xfc /* OpRegion Base */
/*
* MCHBAR
*/
#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x))
#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x))
#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x))
#define MCHBAR32_OR(x, or) MCHBAR32(x) = (MCHBAR32(x) | (or))
#define SSKPD 0x5d14 /* 16bit (scratchpad) */
#define BIOS_RESET_CPL 0x5da8 /* 8bit */
/*
* EPBAR - Egress Port Root Complex Register Block
*/
#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x))
#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x))
#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x))
#define EPPVCCAP1 0x004 /* 32bit */
#define EPPVCCAP2 0x008 /* 32bit */
#define EPVC0RCAP 0x010 /* 32bit */
#define EPVC0RCTL 0x014 /* 32bit */
#define EPVC0RSTS 0x01a /* 16bit */
#define EPVC1RCAP 0x01c /* 32bit */
#define EPVC1RCTL 0x020 /* 32bit */
#define EPVC1RSTS 0x026 /* 16bit */
#define EPVC1MTS 0x028 /* 32bit */
#define EPVC1IST 0x038 /* 64bit */
#define EPESD 0x044 /* 32bit */
#define EPLE1D 0x050 /* 32bit */
#define EPLE1A 0x058 /* 64bit */
#define EPLE2D 0x060 /* 32bit */
#define EPLE2A 0x068 /* 64bit */
#define PORTARB 0x100 /* 256bit */
/*
* DMIBAR
*/
#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x))
#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x))
#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x))
#define DMIVCECH 0x000 /* 32bit */
#define DMIPVCCAP1 0x004 /* 32bit */
#define DMIPVCCAP2 0x008 /* 32bit */
#define DMIPVCCCTL 0x00c /* 16bit */
#define DMIVC0RCAP 0x010 /* 32bit */
#define DMIVC0RCTL0 0x014 /* 32bit */
#define DMIVC0RSTS 0x01a /* 16bit */
#define DMIVC1RCAP 0x01c /* 32bit */
#define DMIVC1RCTL 0x020 /* 32bit */
#define DMIVC1RSTS 0x026 /* 16bit */
#define DMILE1D 0x050 /* 32bit */
#define DMILE1A 0x058 /* 64bit */
#define DMILE2D 0x060 /* 32bit */
#define DMILE2A 0x068 /* 64bit */
#define DMILCAP 0x084 /* 32bit */
#define DMILCTL 0x088 /* 16bit */
#define DMILSTS 0x08a /* 16bit */
#define DMICTL1 0x0f0 /* 32bit */
#define DMICTL2 0x0fc /* 32bit */
#define DMICC 0x208 /* 32bit */
#define DMIDRCCFG 0xeb4 /* 32bit */
#ifndef __ASSEMBLER__
static inline void barrier(void) { asm("" ::: "memory"); }
struct ied_header {
char signature[10];
u32 size;
u8 reserved[34];
} __attribute__ ((packed));
#define PCI_DEVICE_ID_SB 0x0104
#define PCI_DEVICE_ID_IB 0x0154
#ifdef __SMM__
void intel_sandybridge_finalize_smm(void);
#else /* !__SMM__ */
int bridge_silicon_revision(void);
void nehalem_early_initialization(int chipset_type);
void nehalem_late_initialization(void);
/* debugging functions */
void print_pci_devices(void);
void dump_pci_device(unsigned dev);
void dump_pci_devices(void);
void dump_spd_registers(void);
void dump_mem(unsigned start, unsigned end);
void report_platform_info(void);
#endif /* !__SMM__ */
#define MRC_DATA_ALIGN 0x1000
#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24))
struct mrc_data_container {
u32 mrc_signature; // "MRCD"
u32 mrc_data_size; // Actual total size of this structure
u32 mrc_checksum; // IP style checksum
u32 reserved; // For header alignment
u8 mrc_data[0]; // Variable size, platform/run time dependent.
} __attribute__ ((packed));
struct mrc_data_container *find_current_mrc_cache(void);
#if !defined(__PRE_RAM__)
#include "gma.h"
int init_igd_opregion(igd_opregion_t *igd_opregion);
#endif
#endif
#endif
#endif

372
src/northbridge/intel/nehalem/northbridge.c Normal file
View File

@ -0,0 +1,372 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
* Copyright (C) 2013 Vladimir Serbinenko
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <console/console.h>
#include <arch/acpi.h>
#include <arch/io.h>
#include <stdint.h>
#include <delay.h>
#include <cpu/intel/model_2065x/model_2065x.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/hypertransport.h>
#include <stdlib.h>
#include <string.h>
#include <cpu/cpu.h>
#include <cbmem.h>
#include "chip.h"
#include "nehalem.h"
static int bridge_revision_id = -1;
int bridge_silicon_revision(void)
{
if (bridge_revision_id < 0) {
uint8_t stepping = cpuid_eax(1) & 0xf;
uint8_t bridge_id =
pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)),
PCI_DEVICE_ID) & 0xf0;
bridge_revision_id = bridge_id | stepping;
}
return bridge_revision_id;
}
/* Reserve everything between A segment and 1MB:
*
* 0xa0000 - 0xbffff: legacy VGA
* 0xc0000 - 0xcffff: VGA OPROM (needed by kernel)
* 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI
*/
static const int legacy_hole_base_k = 0xa0000 / 1024;
static const int legacy_hole_size_k = 384;
static void add_fixed_resources(struct device *dev, int index)
{
struct resource *resource;
/* 0xe0000000-0xf0000000 PCIe config.
0xfed10000-0xfed14000 MCH
0xfed17000-0xfed18000 HECI
0xfed18000-0xfed19000 DMI
0xfed19000-0xfed1a000 EPBAR
0xfed1c000-0xfed20000 RCBA
0xfed90000-0xfed94000 IOMMU
0xff800000-0xffffffff ROM. */
resource = new_resource(dev, index++);
resource->base = (resource_t) 0xe0000000;
resource->size = (resource_t) 0x10000000;
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
resource = new_resource(dev, index++);
resource->base = (resource_t) 0xfed00000;
resource->size = (resource_t) 0x00100000;
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
mmio_resource(dev, index++, legacy_hole_base_k,
(0xc0000 >> 10) - legacy_hole_base_k);
reserved_ram_resource(dev, index++, 0xc0000 >> 10,
(0x100000 - 0xc0000) >> 10);
#if CONFIG_CHROMEOS_RAMOOPS
reserved_ram_resource(dev, index++,
CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10,
CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10);
#endif
}
static void pci_domain_set_resources(device_t dev)
{
assign_resources(dev->link_list);
}
/* TODO We could determine how many PCIe busses we need in
* the bar. For now that number is hardcoded to a max of 64.
* See e7525/northbridge.c for an example.
*/
static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources,
.enable_resources = NULL,
.init = NULL,
.scan_bus = pci_domain_scan_bus,
.ops_pci_bus = pci_bus_default_ops,
};
static void mc_read_resources(device_t dev)
{
uint32_t tseg_base;
uint64_t TOUUD;
uint16_t reg16;
pci_dev_read_resources(dev);
tseg_base = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), TSEG);
TOUUD = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)),
D0F0_TOUUD);
printk(BIOS_DEBUG, "ram_before_4g_top: 0x%x\n", tseg_base);
printk(BIOS_DEBUG, "TOUUD: 0x%x\n", (unsigned)TOUUD);
/* Report the memory regions */
ram_resource(dev, 3, 0, 640);
ram_resource(dev, 4, 768, ((tseg_base >> 10) - 768));
/* Using uma_resource() here would fail as base & size cannot
* be used as-is for a single MTRR. This would cause excessive
* use of MTRRs.
*
* Use of mmio_resource() instead does not create UC holes by using
* MTRRs, but making these regions uncacheable is taken care of by
* making sure they do not overlap with any ram_resource().
*
* The resources can be changed to use separate mmio_resource()
* calls after MTRR code is able to merge them wisely.
*/
mmio_resource(dev, 5, tseg_base >> 10, CONFIG_SMM_TSEG_SIZE >> 10);
reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), D0F0_GGC);
const int uma_sizes_gtt[16] =
{ 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4, 42, 42, 42, 42 };
/* Igd memory */
const int uma_sizes_igd[16] = {
0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352, 256, 512
};
u32 igd_base, gtt_base;
int uma_size_igd, uma_size_gtt;
uma_size_igd = uma_sizes_igd[(reg16 >> 4) & 0xF];
uma_size_gtt = uma_sizes_gtt[(reg16 >> 8) & 0xF];
igd_base =
pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), D0F0_IGD_BASE);
gtt_base =
pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), D0F0_GTT_BASE);
mmio_resource(dev, 6, gtt_base >> 10, uma_size_gtt << 10);
mmio_resource(dev, 7, igd_base >> 10, uma_size_igd << 10);
if (TOUUD > 4096)
ram_resource(dev, 8, (4096 << 10), ((TOUUD - 4096) << 10));
/* This memory is not DMA-capable. */
if (TOUUD >= 8192 - 64)
bad_ram_resource(dev, 9, 0x1fc000000ULL >> 10, 0x004000000 >> 10);
add_fixed_resources(dev, 10);
set_top_of_ram(tseg_base);
}
static void mc_set_resources(device_t dev)
{
/* And call the normal set_resources */
pci_dev_set_resources(dev);
}
static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor &
0xffff));
}
}
static void northbridge_dmi_init(struct device *dev)
{
u32 reg32;
/* Clear error status bits */
DMIBAR32(0x1c4) = 0xffffffff;
DMIBAR32(0x1d0) = 0xffffffff;
/* Steps prior to DMI ASPM */
if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
reg32 = DMIBAR32(0x250);
reg32 &= ~((1 << 22) | (1 << 20));
reg32 |= (1 << 21);
DMIBAR32(0x250) = reg32;
}
reg32 = DMIBAR32(0x238);
reg32 |= (1 << 29);
DMIBAR32(0x238) = reg32;
if (bridge_silicon_revision() >= SNB_STEP_D0) {
reg32 = DMIBAR32(0x1f8);
reg32 |= (1 << 16);
DMIBAR32(0x1f8) = reg32;
} else if (bridge_silicon_revision() >= SNB_STEP_D1) {
reg32 = DMIBAR32(0x1f8);
reg32 &= ~(1 << 26);
reg32 |= (1 << 16);
DMIBAR32(0x1f8) = reg32;
reg32 = DMIBAR32(0x1fc);
reg32 |= (1 << 12) | (1 << 23);
DMIBAR32(0x1fc) = reg32;
}
/* Enable ASPM on SNB link, should happen before PCH link */
if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
reg32 = DMIBAR32(0xd04);
reg32 |= (1 << 4);
DMIBAR32(0xd04) = reg32;
}
reg32 = DMIBAR32(0x88);
reg32 |= (1 << 1) | (1 << 0);
DMIBAR32(0x88) = reg32;
}
static void northbridge_init(struct device *dev)
{
u8 bios_reset_cpl;
u32 bridge_type;
northbridge_dmi_init(dev);
bridge_type = MCHBAR32(0x5f10);
bridge_type &= ~0xff;
if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
/* Enable Power Aware Interrupt Routing */
u8 pair = MCHBAR8(0x5418);
pair &= ~0xf; /* Clear 3:0 */
pair |= 0x4; /* Fixed Priority */
MCHBAR8(0x5418) = pair;
/* 30h for IvyBridge */
bridge_type |= 0x30;
} else {
/* 20h for Sandybridge */
bridge_type |= 0x20;
}
MCHBAR32(0x5f10) = bridge_type;
/*
* Set bit 0 of BIOS_RESET_CPL to indicate to the CPU
* that BIOS has initialized memory and power management
*/
bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL);
bios_reset_cpl |= 1;
MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl;
printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n");
/* Configure turbo power limits 1ms after reset complete bit */
mdelay(1);
#ifdef DISABLED
set_power_limits(28);
/*
* CPUs with configurable TDP also need power limits set
* in MCHBAR. Use same values from MSR_PKG_POWER_LIMIT.
*/
if (cpu_config_tdp_levels()) {
msr_t msr = rdmsr(MSR_PKG_POWER_LIMIT);
MCHBAR32(0x59A0) = msr.lo;
MCHBAR32(0x59A4) = msr.hi;
}
#endif
/* Set here before graphics PM init */
MCHBAR32(0x5500) = 0x00100001;
}
static void northbridge_enable(device_t dev)
{
#if CONFIG_HAVE_ACPI_RESUME
switch (pci_read_config32(dev, SKPAD)) {
case 0xcafebabe:
printk(BIOS_DEBUG, "Normal boot.\n");
acpi_slp_type = 0;
break;
case 0xcafed00d:
printk(BIOS_DEBUG, "S3 Resume.\n");
acpi_slp_type = 3;
break;
default:
printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n");
acpi_slp_type = 0;
break;
}
#endif
}
static struct pci_operations intel_pci_ops = {
.set_subsystem = intel_set_subsystem,
};
static struct device_operations mc_ops = {
.read_resources = mc_read_resources,
.set_resources = mc_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = northbridge_init,
.enable = northbridge_enable,
.scan_bus = 0,
.ops_pci = &intel_pci_ops,
};
static const struct pci_driver mc_driver_44 __pci_driver = {
.ops = &mc_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = 0x0044, /* Nehalem */
};
static void cpu_bus_init(device_t dev)
{
initialize_cpus(dev->link_list);
/* Enable ROM caching if option was selected. */
x86_mtrr_enable_rom_caching();
}
static void cpu_bus_noop(device_t dev)
{
}
static struct device_operations cpu_bus_ops = {
.read_resources = cpu_bus_noop,
.set_resources = cpu_bus_noop,
.enable_resources = cpu_bus_noop,
.init = cpu_bus_init,
.scan_bus = 0,
};
static void enable_dev(device_t dev)
{
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN) {
dev->ops = &pci_domain_ops;
} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
dev->ops = &cpu_bus_ops;
}
}
struct chip_operations northbridge_intel_nehalem_ops = {
CHIP_NAME("Intel i7 (Nehalem) integrated Northbridge")
.enable_dev = enable_dev,
};

5019
src/northbridge/intel/nehalem/raminit.c Normal file
View File

File diff suppressed because it is too large Load Diff

27
src/northbridge/intel/nehalem/raminit.h Normal file
View File

@ -0,0 +1,27 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Vladimir Serbinenko
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef RAMINIT_H
#define RAMINIT_H
#include "nehalem.h"
void raminit(int s3resume);
#endif /* RAMINIT_H */

1278
src/northbridge/intel/nehalem/raminit_tables.c Normal file
View File

File diff suppressed because it is too large Load Diff