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sb/intel: Replace DTS2 with FLVL 

Replace the unused DTS2 field with FLVL (fan level).
Required to use the fan level on all thinkpads to store and retrieve the
current fan level.

Possible additional use case is to modify the fan level from a SMI handler.

Change-Id: I1ee5348d24b018ab1b61067813c1db63d6706c12
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/22513
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
This commit is contained in:
Patrick Rudolph 2017-11-13 18:57:54 +01:00
parent bfbe78caec
commit c6fa12727a
6 changed files with 6 additions and 6 deletions
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2
src/southbridge/intel/i82801gx/acpi/globalnvs.asl
View File

@ -57,7 +57,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
TCRT, 8, // 0x19 - critical trip point
DTSE, 8, // 0x1a - Digital Thermal Sensor enable
DTS1, 8, // 0x1b - DT sensor 1
DTS2, 8, // 0x1c - DT sensor 2
FLVL, 8, // 0x1c - current fan level
/* Battery Support */
Offset (0x1e),
BNUM, 8, // 0x1e - number of batteries

2
src/southbridge/intel/i82801gx/nvs.h
View File

@ -42,7 +42,7 @@ typedef struct {
u8 tcrt; /* 0x19 - critical trip point */
u8 dtse; /* 0x1a - Digital Thermal Sensor enable */
u8 dts1; /* 0x1b - DT sensor 1 */
u8 dts2; /* 0x1c - DT sensor 2 */
u8 flvl; /* 0x1c - current fan level */
u8 rsvd2;
/* Battery Support */
u8 bnum; /* 0x1e - number of batteries */

2
src/southbridge/intel/i82801ix/acpi/globalnvs.asl
View File

@ -58,7 +58,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
TCRT, 8, // 0x19 - critical trip point
DTSE, 8, // 0x1a - Digital Thermal Sensor enable
DTS1, 8, // 0x1b - DT sensor 1
DTS2, 8, // 0x1c - DT sensor 2
FLVL, 8, // 0x1c - current fan level
/* Battery Support */
Offset (0x1e),
BNUM, 8, // 0x1e - number of batteries

2
src/southbridge/intel/i82801ix/nvs.h
View File

@ -42,7 +42,7 @@ typedef struct {
u8 tcrt; /* 0x19 - critical trip point */
u8 dtse; /* 0x1a - Digital Thermal Sensor enable */
u8 dts1; /* 0x1b - DT sensor 1 */
u8 dts2; /* 0x1c - DT sensor 2 */
u8 flvl; /* 0x1c - current fan level */
u8 rsvd2;
/* Battery Support */
u8 bnum; /* 0x1e - number of batteries */

2
src/southbridge/intel/i82801jx/acpi/globalnvs.asl
View File

@ -58,7 +58,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
CRTT, 8, // 0x19 - critical trip point
DTSE, 8, // 0x1a - Digital Thermal Sensor enable
DTS1, 8, // 0x1b - DT sensor 1
DTS2, 8, // 0x1c - DT sensor 2
FLVL, 8, // 0x1c - current fan level
/* Battery Support */
Offset (0x1e),
BNUM, 8, // 0x1e - number of batteries

2
src/southbridge/intel/i82801jx/nvs.h
View File

@ -42,7 +42,7 @@ typedef struct {
u8 crtt; /* 0x19 - critical trip point */
u8 dtse; /* 0x1a - Digital Thermal Sensor enable */
u8 dts1; /* 0x1b - DT sensor 1 */
u8 dts2; /* 0x1c - DT sensor 2 */
u8 flvl; /* 0x1c - current fan level */
u8 rsvd2;
/* Battery Support */
u8 bnum; /* 0x1e - number of batteries */