device: Use pcidev_on_root()

Change-Id: Icf34b39d80f6e46d32a39b68f38fb2752c0bcebc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/26484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

src/cpu/amd/family_10h-family_15h/model_10xxx_init.c

@@ -142,7 +142,8 @@ static void model_10xxx_init(struct device *dev)
 		uint32_t f5x80;
 		uint8_t enabled;
 		uint8_t compute_unit_count = 0;
-		f5x80 = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18 + id.nodeid, 5)), 0x80);
+		f5x80 = pci_read_config32(pcidev_on_root(0x18 + id.nodeid, 5),
+									0x80);
 		enabled = f5x80 & 0xf;
 		if (enabled == 0x1)
 			compute_unit_count = 1;
@@ -161,11 +162,13 @@ static void model_10xxx_init(struct device *dev)
 		uint32_t f0x160;
 		uint8_t core_count = 0;
 		uint8_t node_count = 0;
-		f0x60 = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18 + id.nodeid, 0)), 0x60);
+		f0x60 = pci_read_config32(pcidev_on_root(0x18 + id.nodeid, 0),
+									0x60);
 		core_count = (f0x60 >> 16) & 0x1f;
 		node_count = ((f0x60 >> 4) & 0x7) + 1;
 		if (is_gt_rev_d()) {
-			f0x160 = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18 + id.nodeid, 0)), 0x160);
+			f0x160 = pci_read_config32(
+				   pcidev_on_root(0x18 + id.nodeid, 0), 0x160);
 			core_count |= ((f0x160 >> 16) & 0x7) << 5;
 		}
 		core_count++;

src/cpu/amd/family_10h-family_15h/monotonic_timer.c

@@ -51,7 +51,8 @@ static void init_timer(void)
 
 	/* Get boost capability */
 	if ((model == 0x8) || (model == 0x9)) {	/* revision D */
-		boost_capable = (pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 4)), 0x15c) & 0x4) >> 2;
+		boost_capable = (pci_read_config32(pcidev_on_root(0x18, 4),
+							    0x15c) & 0x4) >> 2;
 	}
 
 	/* Set up TSC (BKDG v3.62 section 2.9.4)*/

src/cpu/amd/family_10h-family_15h/powernow_acpi.c

@@ -233,16 +233,17 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
 	fam15h = !!(mctGetLogicalCPUID(0) & AMD_FAM15_ALL);
 	/* Get number of cores */
 	if (fam15h) {
-		cmp_cap = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 5)), 0x84) & 0xff;
+		cmp_cap = pci_read_config32(pcidev_on_root(0x18, 5), 0x84) &
+									  0xff;
 	} else {
-		dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xe8);
+		dtemp = pci_read_config32(pcidev_on_root(0x18, 3), 0xe8);
 		cmp_cap = (dtemp & 0x3000) >> 12;
 		if (mctGetLogicalCPUID(0) & (AMD_FAM10_REV_D | AMD_FAM15_ALL))	/* revision D or higher */
 			cmp_cap |= (dtemp & 0x8000) >> 13;
 	}
 
 	/* Get number of nodes */
-	dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 0)), 0x60);
+	dtemp = pci_read_config32(pcidev_on_root(0x18, 0), 0x60);
 	node_count = ((dtemp & 0x70) >> 4) + 1;
 	cores_per_node = cmp_cap + 1;
 
@@ -251,7 +252,7 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
 
 	/* Get number of boost states */
 	uint8_t boost_count = 0;
-	dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 4)), 0x15c);
+	dtemp = pci_read_config32(pcidev_on_root(0x18, 4), 0x15c);
 	if (fam10h_rev_e)
 		boost_count = (dtemp >> 2) & 0x1;
 	else if (mctGetLogicalCPUID(0) & AMD_FAM15_ALL)
@@ -289,7 +290,7 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
 	uint8_t single_link;
 
 	/* Determine if this is a PVI or SVI system */
-	dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xA0);
+	dtemp = pci_read_config32(pcidev_on_root(0x18, 3), 0xA0);
 
 	if (dtemp & PVI_MODE)
 		pviModeFlag = 1;
@@ -361,10 +362,10 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
 		core_power = (core_voltage * cpuidd) / (expanded_cpuidv * 10);
 
 		/* Calculate transition latency */
-		dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xD4);
+		dtemp = pci_read_config32(pcidev_on_root(0x18, 3), 0xD4);
 		power_step_up = (dtemp & 0xf000000) >> 24;
 		power_step_down = (dtemp & 0xf00000) >> 20;
-		dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xA0);
+		dtemp = pci_read_config32(pcidev_on_root(0x18, 3), 0xA0);
 		pll_lock_time = (dtemp & 0x3800) >> 11;
 		if (all_enabled_cores_have_same_cpufid)
 			core_latency = ((12 * power_step_down) + power_step_up) / 1000;
@@ -396,7 +397,7 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
 	for (index = 0; index < total_core_count; index++) {
 		/* Determine if this is a single-link processor */
 		node_index = 0x18 + (index / cores_per_node);
-		dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(node_index, 0)), 0x80);
+		dtemp = pci_read_config32(pcidev_on_root(node_index, 0), 0x80);
 		single_link = !!(((dtemp & 0xff00) >> 8) == 0);
 
 		/* Enter processor core scope */

src/cpu/amd/family_10h-family_15h/processor_name.c

@@ -235,7 +235,7 @@ int init_processor_name(void)
 	if (fam15h) {
 		/* Family 15h or later */
 		uint32_t dword;
-		struct device *cpu_fn5_dev = dev_find_slot(0, PCI_DEVFN(0x18, 5));
+		struct device *cpu_fn5_dev = pcidev_on_root(0x18, 5);
 		pci_write_config32(cpu_fn5_dev, 0x194, 0);
 		dword = pci_read_config32(cpu_fn5_dev, 0x198);
 		if (dword == 0) {

src/cpu/amd/family_10h-family_15h/ram_calc.c

@@ -72,7 +72,7 @@ uint64_t get_cc6_memory_size()
 		if (pci_read_config32(PCI_DEV(0, 0x18, 2), 0x118) & (0x1 << 18))
 			enable_cc6 = 1;
 #else
-		struct device *dct_dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
+		struct device *dct_dev = pcidev_on_root(0x18, 2);
 		if (pci_read_config32(dct_dev, 0x118) & (0x1 << 18))
 			enable_cc6 = 1;
 #endif

src/cpu/intel/haswell/smmrelocate.c

@@ -308,7 +308,7 @@ static void setup_ied_area(struct smm_relocation_params *params)
 void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
 				size_t *smm_save_state_size)
 {
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	struct device *dev = pcidev_on_root(0, 0);
 
 	printk(BIOS_DEBUG, "Setting up SMI for CPU\n");
 
@@ -362,6 +362,6 @@ void smm_lock(void)
 	 * make the SMM registers writable again.
 	 */
 	printk(BIOS_DEBUG, "Locking SMM.\n");
-	pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
+	pci_write_config8(pcidev_on_root(0, 0), SMRAM,
 			D_LCK | G_SMRAME | C_BASE_SEG);
 }

src/drivers/intel/gma/opregion.c

@@ -77,7 +77,7 @@ void intel_gma_opregion_register(uintptr_t opregion)
 	u16 reg16;
 	u16 sci_reg;
 
-	igd = dev_find_slot(0, PCI_DEVFN(0x2, 0));
+	igd = pcidev_on_root(0x2, 0);
 	if (!igd || !igd->enabled)
 		return;
 
@@ -228,7 +228,7 @@ static enum cb_err locate_vbt_cbfs(struct region_device *rdev)
 static enum cb_err locate_vbt_vbios_cbfs(struct region_device *rdev)
 {
 	const u8 *oprom =
-		(const u8 *)pci_rom_probe(dev_find_slot(0, PCI_DEVFN(0x2, 0)));
+		(const u8 *)pci_rom_probe(pcidev_on_root(0x2, 0));
 	if (oprom == NULL)
 		return CB_ERR;
 

src/mainboard/amd/bettong/BiosCallOuts.c

@@ -120,7 +120,7 @@ static AGESA_STATUS board_ReadSpd(UINT32 Func, UINTN Data, VOID *ConfigPtr)
 	int spdAddress;
 	AGESA_READ_SPD_PARAMS *info = ConfigPtr;
 
-	DEVTREE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
+	DEVTREE_CONST struct device *dev = pcidev_on_root(0x18, 2);
 	DEVTREE_CONST struct northbridge_amd_pi_00660F01_config *config = dev->chip_info;
 	UINT8 spdAddrLookup_rev_F [2][2][4]= {
 		{ {0xA0, 0xA2}, {0xA4, 0xAC}, }, /* socket 0 - Channel 0 & 1 - 8-bit SPD addresses */

src/mainboard/amd/bettong/mptable.c

@@ -108,7 +108,7 @@ static void *smp_write_config_table(void *v)
 	/* on board NIC & Slot PCIE.  */
 
 	/* PCI slots */
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+	struct device *dev = pcidev_on_root(0x14, 4);
 	if (dev && dev->enabled) {
 		u8 bus_pci = dev->link_list->secondary;
 		/* PCI_SLOT 0. */

src/mainboard/amd/gardenia/mptable.c

@@ -113,7 +113,7 @@ static void *smp_write_config_table(void *v)
 	/* on board NIC & Slot PCIE.  */
 
 	/* PCI slots */
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+	struct device *dev = pcidev_on_root(0x14, 4);
 	if (dev && dev->enabled) {
 		u8 bus_pci = dev->link_list->secondary;
 		/* PCI_SLOT 0. */

src/mainboard/amd/inagua/mptable.c

@@ -101,7 +101,7 @@ static void *smp_write_config_table(void *v)
 	/* on board NIC & Slot PCIE.  */
 
 	/* PCI slots */
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+	struct device *dev = pcidev_on_root(0x14, 4);
 	if (dev && dev->enabled) {
 		u8 bus_pci = dev->link_list->secondary;
 		/* PCI_SLOT 0. */

src/mainboard/amd/mahogany_fam10/mainboard.c

@@ -31,7 +31,7 @@ void set_pcie_dereset(void)
 	u16 word;
 	struct device *sm_dev;
 	/* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
-	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	sm_dev = pcidev_on_root(0x14, 0);
 
 	word = pci_read_config16(sm_dev, 0xA8);
 	word |= (1 << 0) | (1 << 2);	/* Set Gpio6,4 as output */
@@ -44,7 +44,7 @@ void set_pcie_reset(void)
 	u16 word;
 	struct device *sm_dev;
 	/* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
-	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	sm_dev = pcidev_on_root(0x14, 0);
 
 	word = pci_read_config16(sm_dev, 0xA8);
 	word &= ~((1 << 0) | (1 << 2));	/* Set Gpio6,4 as output */
@@ -64,13 +64,13 @@ static void get_ide_dma66(void)
 	/*u32 sm_dev, ide_dev; */
 	struct device *sm_dev, ide_dev;
 
-	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	sm_dev = pcidev_on_root(0x14, 0);
 
 	byte = pci_read_config8(sm_dev, 0xA9);
 	byte |= (1 << 5);	/* Set Gpio9 as input */
 	pci_write_config8(sm_dev, 0xA9, byte);
 
-	ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
+	ide_dev = pcidev_on_root(0x14, 1);
 	byte = pci_read_config8(ide_dev, 0x56);
 	byte &= ~(7 << 0);
 	if ((1 << 5) & pci_read_config8(sm_dev, 0xAA))

src/mainboard/amd/olivehill/mptable.c

@@ -175,7 +175,7 @@ static void *smp_write_config_table(void *v)
 	/* on board NIC & Slot PCIE.  */
 
 	/* PCI slots */
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+	struct device *dev = pcidev_on_root(0x14, 4);
 	if (dev && dev->enabled) {
 		u8 bus_pci = dev->link_list->secondary;
 		/* PCI_SLOT 0. */

src/mainboard/amd/olivehillplus/mptable.c

@@ -136,7 +136,7 @@ static void *smp_write_config_table(void *v)
 	/* on board NIC & Slot PCIE.  */
 
 	/* PCI slots */
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+	struct device *dev = pcidev_on_root(0x14, 4);
 	if (dev && dev->enabled) {
 		u8 bus_pci = dev->link_list->secondary;
 		/* PCI_SLOT 0. */

src/mainboard/amd/parmer/mptable.c

@@ -136,7 +136,7 @@ static void *smp_write_config_table(void *v)
 	/* on board NIC & Slot PCIE.  */
 
 	/* PCI slots */
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+	struct device *dev = pcidev_on_root(0x14, 4);
 	if (dev && dev->enabled) {
 		u8 bus_pci = dev->link_list->secondary;
 		/* PCI_SLOT 0. */

src/mainboard/amd/persimmon/mptable.c

@@ -106,7 +106,7 @@ static void *smp_write_config_table(void *v)
 	PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]);	/* Use INTE */
 
 	/* PCI slots */
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+	struct device *dev = pcidev_on_root(0x14, 4);
 	if (dev && dev->enabled) {
 		u8 bus_pci = dev->link_list->secondary;
 		/* PCI_SLOT 0 */

src/mainboard/amd/south_station/mptable.c

@@ -97,7 +97,7 @@ static void *smp_write_config_table(void *v)
 	/* on board NIC & Slot PCIE.  */
 
 	/* PCI slots */
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+	struct device *dev = pcidev_on_root(0x14, 4);
 	if (dev && dev->enabled) {
 		u8 bus_pci = dev->link_list->secondary;
 		/* PCI_SLOT 0. */

src/mainboard/amd/thatcher/mptable.c

@@ -136,7 +136,7 @@ static void *smp_write_config_table(void *v)
 	/* on board NIC & Slot PCIE.  */
 
 	/* PCI slots */
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+	struct device *dev = pcidev_on_root(0x14, 4);
 	if (dev && dev->enabled) {
 		u8 bus_pci = dev->link_list->secondary;
 		/* PCI_SLOT 0. */

src/mainboard/amd/tilapia_fam10/mainboard.c

@@ -50,7 +50,7 @@ void set_pcie_dereset(void)
 	pm_iowrite(0x94, byte);
 
 	/* set the GPIO65 output enable and the value is 1 */
-	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	sm_dev = pcidev_on_root(0x14, 0);
 	word = pci_read_config16(sm_dev, 0x7e);
 	word |= (1 << 0);
 	word &= ~(1 << 4);
@@ -76,7 +76,7 @@ void set_pcie_reset(void)
 	pm_iowrite(0x94, byte);
 
 	/* set the GPIO65 output enable and the value is 0 */
-	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	sm_dev = pcidev_on_root(0x14, 0);
 	word = pci_read_config16(sm_dev, 0x7e);
 	word &= ~(1 << 0);
 	word &= ~(1 << 4);
@@ -92,7 +92,7 @@ int is_dev3_present(void)
 	struct device *sm_dev;
 
 	/* access the smbus extended register */
-	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	sm_dev = pcidev_on_root(0x14, 0);
 
 	/* put the GPIO68 output to tristate */
 	word = pci_read_config16(sm_dev, 0x7e);
@@ -130,7 +130,7 @@ static void set_gpio40_gfx(void)
 	pm2_iowrite(0xf1, byte);
 
 	/* access the smbus extended register */
-	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	sm_dev = pcidev_on_root(0x14, 0);
 
 	/*if the dev3 is present, set the gfx to 2x8 lanes*/
 	/*otherwise set the gfx to 1x16 lanes*/
@@ -190,7 +190,7 @@ static void set_thermal_config(void)
 	pm2_iowrite(0x42, byte);
 
 	/* set GPIO 64 to input */
-	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	sm_dev = pcidev_on_root(0x14, 0);
 	word = pci_read_config16(sm_dev, 0x56);
 	word |= 1 << 7;
 	pci_write_config16(sm_dev, 0x56, word);

src/mainboard/amd/torpedo/mptable.c

@@ -179,7 +179,7 @@ static void *smp_write_config_table(void *v)
 	/* on board NIC & Slot PCIE.  */
 
 	/* PCI slots */
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+	struct device *dev = pcidev_on_root(0x14, 4);
 	if (dev && dev->enabled) {
 		u8 bus_pci = dev->link_list->secondary;
 

src/mainboard/amd/union_station/mptable.c

@@ -97,7 +97,7 @@ static void *smp_write_config_table(void *v)
 	/* on board NIC & Slot PCIE.  */
 
 	/* PCI slots */
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+	struct device *dev = pcidev_on_root(0x14, 4);
 	if (dev && dev->enabled) {
 		u8 bus_pci = dev->link_list->secondary;
 		/* PCI_SLOT 0. */

src/mainboard/aopen/dxplplusu/fadt.c

@@ -32,7 +32,7 @@
 void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 {
 	acpi_header_t *header = &(fadt->header);
-	u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe;
+	u16 pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffe;
 
 	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
 	memcpy(header->signature, "FACP", 4);

src/mainboard/asrock/e350m1/mptable.c

@@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v)
 	/* on board NIC & Slot PCIE.  */
 
 	/* PCI slots */
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+	struct device *dev = pcidev_on_root(0x14, 4);
 	if (dev && dev->enabled) {
 		u8 bus_pci = dev->link_list->secondary;
 		/* PCI_SLOT 0. */

src/mainboard/asrock/imb-a180/mptable.c

@@ -176,7 +176,7 @@ static void *smp_write_config_table(void *v)
 	/* on board NIC & Slot PCIE.  */
 
 	/* PCI slots */
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+	struct device *dev = pcidev_on_root(0x14, 4);
 	if (dev && dev->enabled) {
 		u8 bus_pci = dev->link_list->secondary;
 		/* PCI_SLOT 0. */

src/mainboard/asus/f2a85-m/mptable.c

@@ -142,7 +142,7 @@ static void *smp_write_config_table(void *v)
 	/* on board NIC & Slot PCIE.  */
 
 	/* PCI slots */
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+	struct device *dev = pcidev_on_root(0x14, 4);
 	if (dev && dev->enabled) {
 		u8 bus_pci = dev->link_list->secondary;
 		/* PCI_SLOT 0. */

src/mainboard/asus/kcma-d8/acpi_tables.c

@@ -41,7 +41,7 @@ unsigned long acpi_fill_madt(unsigned long current)
 					   IO_APIC_ADDR, gsi_base);
 	/* IOAPIC on rs5690 */
 	gsi_base += 24;		/* SB700 has 24 IOAPIC entries. */
-	dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	dev = pcidev_on_root(0, 0);
 	if (dev) {
 		pci_write_config32(dev, 0xF8, 0x1);
 		dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;

src/mainboard/asus/kcma-d8/mainboard.c

@@ -28,7 +28,7 @@ void set_pcie_reset(void)
 {
 	struct device *pcie_core_dev;
 
-	pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	pcie_core_dev = pcidev_on_root(0, 0);
 	set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x28282828);
 	set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x000000FF, 0x00000028);
 }
@@ -37,7 +37,7 @@ void set_pcie_dereset(void)
 {
 	struct device *pcie_core_dev;
 
-	pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	pcie_core_dev = pcidev_on_root(0, 0);
 	set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x6F6F6F6F);
 	set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x000000FF, 0x0000006F);
 }

src/mainboard/asus/kcma-d8/mptable.c

@@ -102,7 +102,7 @@ static void *smp_write_config_table(void *v)
 			 * 00:14.6: INTB MCI
 			 */
 		}
-		dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+		dev = pcidev_on_root(0, 0);
 		if (dev) {
 			pci_write_config32(dev, 0xF8, 0x1);
 			dword_ptr = (u32 *)(pci_read_config32(dev, 0xFC) & 0xfffffff0);
@@ -125,32 +125,32 @@ static void *smp_write_config_table(void *v)
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((11)<<2)|(0)), apicid_sr5650, 30);	/* Device 11 (LNKG, APIC pin 30) */
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((12)<<2)|(0)), apicid_sr5650, 30);	/* Device 12 (LNKG, APIC pin 30) */
 
-	dev = dev_find_slot(0, PCI_DEVFN(0x2, 0));
+	dev = pcidev_on_root(0x2, 0);
 	if (dev && dev->enabled) {
 		uint8_t bus_pci = dev->link_list->secondary;
 		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0x2)|(0)), apicid_sr5650, 0);	/* card behind dev2 */
 	}
-	dev = dev_find_slot(0, PCI_DEVFN(0x4, 0));
+	dev = pcidev_on_root(0x4, 0);
 	if (dev && dev->enabled) {
 		uint8_t bus_pci = dev->link_list->secondary;
 		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0x4)|(0)), apicid_sr5650, 0);	/* PIKE */
 	}
-	dev = dev_find_slot(0, PCI_DEVFN(0x9, 0));
+	dev = pcidev_on_root(0x9, 0);
 	if (dev && dev->enabled) {
 		uint8_t bus_pci = dev->link_list->secondary;
 		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0x9)|(0)), apicid_sr5650, 23);	/* NIC A */
 	}
-	dev = dev_find_slot(0, PCI_DEVFN(0xa, 0));
+	dev = pcidev_on_root(0xa, 0);
 	if (dev && dev->enabled) {
 		uint8_t bus_pci = dev->link_list->secondary;
 		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xa)|(0)), apicid_sr5650, 24);	/* NIC B */
 	}
-	dev = dev_find_slot(0, PCI_DEVFN(0xb, 0));
+	dev = pcidev_on_root(0xb, 0);
 	if (dev && dev->enabled) {
 		uint8_t bus_pci = dev->link_list->secondary;
 		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xb)|(0)), apicid_sr5650, 0);	/* card behind dev11 */
 	}
-	dev = dev_find_slot(0, PCI_DEVFN(0xc, 0));
+	dev = pcidev_on_root(0xc, 0);
 	if (dev && dev->enabled) {
 		uint8_t bus_pci = dev->link_list->secondary;
 		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xc)|(0)), apicid_sr5650, 0);	/* card behind dev12 */
@@ -177,7 +177,7 @@ static void *smp_write_config_table(void *v)
 	PCI_INT(sp5100_bus_number, 0x11, 0x0, 0x16); /* 6, INTG */
 
 	/* PCI slots */
-	dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+	dev = pcidev_on_root(0x14, 4);
 	if (dev && dev->enabled) {
 		u8 bus_pci = dev->link_list->secondary;
 

src/mainboard/asus/kfsn4-dre/acpi_tables.c

@@ -38,7 +38,7 @@ unsigned long acpi_fill_madt(unsigned long current)
 	current = acpi_create_madt_lapics(current);
 
 	/* Write NVIDIA CK804 IOAPIC. */
-	dev = dev_find_slot(0x0, PCI_DEVFN(sysconf.sbdn + 0x1, 0));
+	dev = pcidev_on_root(sysconf.sbdn + 0x1, 0);
 	ASSERT(dev != NULL);
 
 	res = find_resource(dev, PCI_BASE_ADDRESS_1);

src/mainboard/asus/kgpe-d16/acpi_tables.c

@@ -41,7 +41,7 @@ unsigned long acpi_fill_madt(unsigned long current)
 					   IO_APIC_ADDR, gsi_base);
 	/* IOAPIC on rs5690 */
 	gsi_base += 24;		/* SB700 has 24 IOAPIC entries. */
-	dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	dev = pcidev_on_root(0, 0);
 	if (dev) {
 		pci_write_config32(dev, 0xF8, 0x1);
 		dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;

src/mainboard/asus/kgpe-d16/mainboard.c

@@ -28,7 +28,7 @@ void set_pcie_reset(void)
 {
 	struct device *pcie_core_dev;
 
-	pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	pcie_core_dev = pcidev_on_root(0, 0);
 	set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x28282828);
 	set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x000000FF, 0x00000028);
 }
@@ -37,7 +37,7 @@ void set_pcie_dereset(void)
 {
 	struct device *pcie_core_dev;
 
-	pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	pcie_core_dev = pcidev_on_root(0, 0);
 	set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x6F6F6F6F);
 	set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x000000FF, 0x0000006F);
 }

src/mainboard/asus/kgpe-d16/mptable.c

@@ -102,7 +102,7 @@ static void *smp_write_config_table(void *v)
 			 * 00:14.6: INTB MCI
 			 */
 		}
-		dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+		dev = pcidev_on_root(0, 0);
 		if (dev) {
 			pci_write_config32(dev, 0xF8, 0x1);
 			dword_ptr = (u32 *)(pci_read_config32(dev, 0xFC) & 0xfffffff0);
@@ -126,37 +126,37 @@ static void *smp_write_config_table(void *v)
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((12)<<2)|(0)), apicid_sr5650, 30);	/* Device 12 (LNKG, APIC pin 30) */
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_sr5650, 30);	/* Device 13 (LNKG, APIC pin 30)) */
 
-	dev = dev_find_slot(0, PCI_DEVFN(0x2, 0));
+	dev = pcidev_on_root(0x2, 0);
 	if (dev && dev->enabled) {
 		uint8_t bus_pci = dev->link_list->secondary;
 		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0x2)|(0)), apicid_sr5650, 0);	/* card behind dev2 */
 	}
-	dev = dev_find_slot(0, PCI_DEVFN(0x4, 0));
+	dev = pcidev_on_root(0x4, 0);
 	if (dev && dev->enabled) {
 		uint8_t bus_pci = dev->link_list->secondary;
 		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0x4)|(0)), apicid_sr5650, 0);	/* PIKE */
 	}
-	dev = dev_find_slot(0, PCI_DEVFN(0x9, 0));
+	dev = pcidev_on_root(0x9, 0);
 	if (dev && dev->enabled) {
 		uint8_t bus_pci = dev->link_list->secondary;
 		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0x9)|(0)), apicid_sr5650, 23);	/* NIC A */
 	}
-	dev = dev_find_slot(0, PCI_DEVFN(0xa, 0));
+	dev = pcidev_on_root(0xa, 0);
 	if (dev && dev->enabled) {
 		uint8_t bus_pci = dev->link_list->secondary;
 		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xa)|(0)), apicid_sr5650, 24);	/* NIC B */
 	}
-	dev = dev_find_slot(0, PCI_DEVFN(0xb, 0));
+	dev = pcidev_on_root(0xb, 0);
 	if (dev && dev->enabled) {
 		uint8_t bus_pci = dev->link_list->secondary;
 		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xb)|(0)), apicid_sr5650, 0);	/* card behind dev11 */
 	}
-	dev = dev_find_slot(0, PCI_DEVFN(0xc, 0));
+	dev = pcidev_on_root(0xc, 0);
 	if (dev && dev->enabled) {
 		uint8_t bus_pci = dev->link_list->secondary;
 		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xc)|(0)), apicid_sr5650, 0);	/* card behind dev12 */
 	}
-	dev = dev_find_slot(0, PCI_DEVFN(0xd, 0));
+	dev = pcidev_on_root(0xd, 0);
 	if (dev && dev->enabled) {
 		uint8_t bus_pci = dev->link_list->secondary;
 		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xd)|(0)), apicid_sr5650, 0);	/* card behind dev13 */
@@ -183,7 +183,7 @@ static void *smp_write_config_table(void *v)
 	PCI_INT(sp5100_bus_number, 0x11, 0x0, 0x16); /* 6, INTG */
 
 	/* PCI slots */
-	dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+	dev = pcidev_on_root(0x14, 4);
 	if (dev && dev->enabled) {
 		u8 bus_pci = dev->link_list->secondary;
 

src/mainboard/asus/m4a78-em/mainboard.c

@@ -40,7 +40,7 @@ void set_pcie_dereset(void)
 	pm_iowrite(0x94, byte);
 
 	/* set the GPIO65 output enable and the value is 1 */
-	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	sm_dev = pcidev_on_root(0x14, 0);
 	word = pci_read_config16(sm_dev, 0x7e);
 	word |= (1 << 0);
 	word &= ~(1 << 4);
@@ -66,7 +66,7 @@ void set_pcie_reset(void)
 	pm_iowrite(0x94, byte);
 
 	/* set the GPIO65 output enable and the value is 0 */
-	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	sm_dev = pcidev_on_root(0x14, 0);
 	word = pci_read_config16(sm_dev, 0x7e);
 	word &= ~(1 << 0);
 	word &= ~(1 << 4);
@@ -84,7 +84,7 @@ int is_dev3_present(void)
 	struct device *sm_dev;
 
 	/* access the smbus extended register */
-	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	sm_dev = pcidev_on_root(0x14, 0);
 
 	/* put the GPIO68 output to tristate */
 	word = pci_read_config16(sm_dev, 0x7e);

src/mainboard/asus/m4a785-m/mainboard.c

@@ -50,7 +50,7 @@ void set_pcie_dereset(void)
 	pm_iowrite(0x94, byte);
 
 	/* set the GPIO65 output enable and the value is 1 */
-	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	sm_dev = pcidev_on_root(0x14, 0);
 	word = pci_read_config16(sm_dev, 0x7e);
 	word |= (1 << 0);
 	word &= ~(1 << 4);
@@ -76,7 +76,7 @@ void set_pcie_reset(void)
 	pm_iowrite(0x94, byte);
 
 	/* set the GPIO65 output enable and the value is 0 */
-	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	sm_dev = pcidev_on_root(0x14, 0);
 	word = pci_read_config16(sm_dev, 0x7e);
 	word &= ~(1 << 0);
 	word &= ~(1 << 4);
@@ -94,7 +94,7 @@ int is_dev3_present(void)
 	struct device *sm_dev;
 
 	/* access the smbus extended register */
-	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	sm_dev = pcidev_on_root(0x14, 0);
 
 	/* put the GPIO68 output to tristate */
 	word = pci_read_config16(sm_dev, 0x7e);
@@ -136,7 +136,7 @@ static void set_thermal_config(void)
 	pm2_iowrite(0x42, byte);
 
 	/* set GPIO 64 to input */
-	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	sm_dev = pcidev_on_root(0x14, 0);
 	word = pci_read_config16(sm_dev, 0x56);
 	word |= 1 << 7;
 	pci_write_config16(sm_dev, 0x56, word);

src/mainboard/bap/ode_e20XX/mptable.c

@@ -104,7 +104,7 @@ static void *smp_write_config_table(void *v)
 	PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]);
 
 	/* PCI slots */
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+	struct device *dev = pcidev_on_root(0x14, 4);
 	if (dev && dev->enabled) {
 		u8 bus_pci = dev->link_list->secondary;
 		/* PCI_SLOT 0 */

src/mainboard/bap/ode_e21XX/mptable.c

@@ -136,7 +136,7 @@ static void *smp_write_config_table(void *v)
 	/* on board NIC & Slot PCIE.  */
 
 	/* PCI slots */
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+	struct device *dev = pcidev_on_root(0x14, 4);
 	if (dev && dev->enabled) {
 		u8 bus_pci = dev->link_list->secondary;
 		/* PCI_SLOT 0. */

src/mainboard/biostar/a68n_5200/mptable.c

@@ -175,7 +175,7 @@ static void *smp_write_config_table(void *v)
 	/* on board NIC & Slot PCIE.  */
 
 	/* PCI slots */
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+	struct device *dev = pcidev_on_root(0x14, 4);
 	if (dev && dev->enabled) {
 		u8 bus_pci = dev->link_list->secondary;
 		/* PCI_SLOT 0. */

src/mainboard/biostar/am1ml/mptable.c

@@ -104,7 +104,7 @@ static void *smp_write_config_table(void *v)
 	PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]);
 
 	/* PCI slots */
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+	struct device *dev = pcidev_on_root(0x14, 4);
 	if (dev && dev->enabled) {
 		u8 bus_pci = dev->link_list->secondary;
 		/* PCI_SLOT 0 */

src/mainboard/elmex/pcm205400/mptable.c

@@ -106,7 +106,7 @@ static void *smp_write_config_table(void *v)
 	PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]);	/* Use INTE */
 
 	/* PCI slots */
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+	struct device *dev = pcidev_on_root(0x14, 4);
 	if (dev && dev->enabled) {
 		u8 bus_pci = dev->link_list->secondary;
 		/* PCI_SLOT 0 */

src/mainboard/emulation/qemu-q35/acpi_tables.c

@@ -44,7 +44,7 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
 void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 {
 	acpi_header_t *header = &(fadt->header);
-	u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe;
+	u16 pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffe;
 	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
 	memcpy(header->signature, "FACP", 4);
 	header->length = sizeof(acpi_fadt_t);

src/mainboard/getac/p470/mainboard.c

@@ -59,16 +59,16 @@ static void pcie_limit_power(void)
 
 	struct device *dev;
 
-	dev = dev_find_slot(0, PCI_DEVFN(28,0));
+	dev = pcidev_on_root(28, 0);
 	if (dev) pci_write_config32(dev, 0x54, 0x0010a0e0);
 
-	dev = dev_find_slot(0, PCI_DEVFN(28,1));
+	dev = pcidev_on_root(28, 1);
 	if (dev) pci_write_config32(dev, 0x54, 0x0018a0e0);
 
-	dev = dev_find_slot(0, PCI_DEVFN(28,2));
+	dev = pcidev_on_root(28, 2);
 	if (dev) pci_write_config32(dev, 0x54, 0x0020a0e0);
 
-	dev = dev_find_slot(0, PCI_DEVFN(28,3));
+	dev = pcidev_on_root(28, 3);
 	if (dev) pci_write_config32(dev, 0x54, 0x0028a0e0);
 #endif
 }

src/mainboard/gigabyte/ma785gm/mainboard.c

@@ -40,7 +40,7 @@ void set_pcie_dereset(void)
 	pm_iowrite(0x94, byte);
 
 	/* set the GPIO65 output enable and the value is 1 */
-	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	sm_dev = pcidev_on_root(0x14, 0);
 	word = pci_read_config16(sm_dev, 0x7e);
 	word |= (1 << 0);
 	word &= ~(1 << 4);
@@ -66,7 +66,7 @@ void set_pcie_reset(void)
 	pm_iowrite(0x94, byte);
 
 	/* set the GPIO65 output enable and the value is 0 */
-	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	sm_dev = pcidev_on_root(0x14, 0);
 	word = pci_read_config16(sm_dev, 0x7e);
 	word &= ~(1 << 0);
 	word &= ~(1 << 4);
@@ -106,7 +106,7 @@ static void set_gpio40_gfx(void)
 	pm2_iowrite(0xf1, byte);
 
 	/* access the smbus extended register */
-	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	sm_dev = pcidev_on_root(0x14, 0);
 
 	/* set the gfx to 1x16 lanes */
 	printk(BIOS_INFO, "Dev3 is not present. GFX Configuration is One x16 slot\n");

src/mainboard/gigabyte/ma785gmt/mainboard.c

@@ -50,7 +50,7 @@ void set_pcie_dereset(void)
 	pm_iowrite(0x94, byte);
 
 	/* set the GPIO65 output enable and the value is 1 */
-	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	sm_dev = pcidev_on_root(0x14, 0);
 	word = pci_read_config16(sm_dev, 0x7e);
 	word |= (1 << 0);
 	word &= ~(1 << 4);
@@ -76,7 +76,7 @@ void set_pcie_reset(void)
 	pm_iowrite(0x94, byte);
 
 	/* set the GPIO65 output enable and the value is 0 */
-	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	sm_dev = pcidev_on_root(0x14, 0);
 	word = pci_read_config16(sm_dev, 0x7e);
 	word &= ~(1 << 0);
 	word &= ~(1 << 4);
@@ -92,7 +92,7 @@ int is_dev3_present(void)
 	struct device *sm_dev;
 
 	/* access the smbus extended register */
-	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	sm_dev = pcidev_on_root(0x14, 0);
 
 	/* put the GPIO68 output to tristate */
 	word = pci_read_config16(sm_dev, 0x7e);
@@ -130,7 +130,7 @@ static void set_gpio40_gfx(void)
 	pm2_iowrite(0xf1, byte);
 
 	/* access the smbus extended register */
-	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	sm_dev = pcidev_on_root(0x14, 0);
 
 	/*if the dev3 is present, set the gfx to 2x8 lanes*/
 	/*otherwise set the gfx to 1x16 lanes*/
@@ -190,7 +190,7 @@ static void set_thermal_config(void)
 	pm2_iowrite(0x42, byte);
 
 	/* set GPIO 64 to input */
-	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	sm_dev = pcidev_on_root(0x14, 0);
 	word = pci_read_config16(sm_dev, 0x56);
 	word |= 1 << 7;
 	pci_write_config16(sm_dev, 0x56, word);

src/mainboard/gigabyte/ma78gm/mainboard.c

@@ -32,7 +32,7 @@ void set_pcie_dereset(void)
 	u16 word;
 	struct device *sm_dev;
 	/* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
-	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	sm_dev = pcidev_on_root(0x14, 0);
 
 	word = pci_read_config16(sm_dev, 0xA8);
 	word |= (1 << 0) | (1 << 2);	/* Set Gpio6,4 as output */
@@ -45,7 +45,7 @@ void set_pcie_reset(void)
 	u16 word;
 	struct device *sm_dev;
 	/* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
-	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	sm_dev = pcidev_on_root(0x14, 0);
 
 	word = pci_read_config16(sm_dev, 0xA8);
 	word &= ~((1 << 0) | (1 << 2));	/* Set Gpio6,4 as output */

src/mainboard/gizmosphere/gizmo/mainboard.c

@@ -52,7 +52,7 @@ static void mainboard_final(void *chip_info)
 	uintptr_t ABAR;
 	u8 *memptr;
 
-	ahci_dev = dev_find_slot(0, PCI_DEVFN(0x11, 0));
+	ahci_dev = pcidev_on_root(0x11, 0);
 	ABAR = pci_read_config32(ahci_dev, 0x24);
 	ABAR &= 0xFFFFFC00;
 	memptr = (u8 *)(ABAR + 0x100 + 0x80 + 0x2C); /* we're on the 2nd port */

src/mainboard/gizmosphere/gizmo/mptable.c

@@ -98,7 +98,7 @@ static void *smp_write_config_table(void *v)
 	/* on board NIC & Slot PCIE.	*/
 
 	/* PCI slots */
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+	struct device *dev = pcidev_on_root(0x14, 4);
 	if (dev && dev->enabled) {
 		u8 bus_pci = dev->link_list->secondary;
 		/* PCI_SLOT 0. */

src/mainboard/gizmosphere/gizmo2/mptable.c

@@ -104,7 +104,7 @@ static void *smp_write_config_table(void *v)
 	PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]);
 
 	/* PCI slots */
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+	struct device *dev = pcidev_on_root(0x14, 4);
 	if (dev && dev->enabled) {
 		u8 bus_pci = dev->link_list->secondary;
 		/* PCI_SLOT 0 */

src/mainboard/google/kahlee/mptable.c

@@ -113,7 +113,7 @@ static void *smp_write_config_table(void *v)
 	/* on board NIC & Slot PCIE.  */
 
 	/* PCI slots */
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+	struct device *dev = pcidev_on_root(0x14, 4);
 	if (dev && dev->enabled) {
 		u8 bus_pci = dev->link_list->secondary;
 		/* PCI_SLOT 0. */

src/mainboard/google/link/mainboard.c

@@ -151,7 +151,7 @@ static void mainboard_init(struct device *dev)
 		/* If running on proto1 - enable reversion of gpio11. */
 		u32 gpio_inv;
 		u16 gpio_base = pci_read_config16
-			(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_BASE) &
+			(pcidev_on_root(0x1f, 0), GPIO_BASE) &
 			0xfffc;
 		u16 gpio_inv_addr = gpio_base + GPI_INV;
 		gpio_inv = inl(gpio_inv_addr);

src/mainboard/google/link/romstage.c

@@ -39,7 +39,7 @@ void pch_enable_lpc(void)
 	const struct device *lpc;
 	const struct southbridge_intel_bd82x6x_config *config = NULL;
 
-	lpc = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
+	lpc = pcidev_on_root(0x1f, 0);
 	if (!lpc)
 		return;
 	if (lpc->chip_info)

src/mainboard/hp/abm/mptable.c

@@ -175,7 +175,7 @@ static void *smp_write_config_table(void *v)
 	/* on board NIC & Slot PCIE.  */
 
 	/* PCI slots */
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+	struct device *dev = pcidev_on_root(0x14, 4);
 	if (dev && dev->enabled) {
 		u8 bus_pci = dev->link_list->secondary;
 		/* PCI_SLOT 0. */

src/mainboard/hp/pavilion_m6_1035dx/mptable.c

@@ -142,7 +142,7 @@ static void *smp_write_config_table(void *v)
 	/* on board NIC & Slot PCIE.  */
 
 	/* PCI slots */
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+	struct device *dev = pcidev_on_root(0x14, 4);
 	if (dev && dev->enabled) {
 		u8 bus_pci = dev->link_list->secondary;
 		/* PCI_SLOT 0. */

src/mainboard/jetway/nf81-t56n-lf/mptable.c

@@ -110,7 +110,7 @@ static void *smp_write_config_table(void *v)
 	PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]);	/* Use INTE */
 
 	/* PCI slots */
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+	struct device *dev = pcidev_on_root(0x14, 4);
 	if (dev && dev->enabled) {
 		u8 bus_pci = dev->link_list->secondary;
 		/* PCI_SLOT 0 */

src/mainboard/jetway/pa78vm5/mainboard.c

@@ -32,7 +32,7 @@ void set_pcie_dereset(void)
 	u16 word;
 	struct device *sm_dev;
 	/* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
-	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	sm_dev = pcidev_on_root(0x14, 0);
 
 	word = pci_read_config16(sm_dev, 0xA8);
 	word |= (1 << 0) | (1 << 2);	/* Set Gpio6,4 as output */
@@ -45,7 +45,7 @@ void set_pcie_reset(void)
 	u16 word;
 	struct device *sm_dev;
 	/* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
-	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	sm_dev = pcidev_on_root(0x14, 0);
 
 	word = pci_read_config16(sm_dev, 0xA8);
 	word &= ~((1 << 0) | (1 << 2));	/* Set Gpio6,4 as output */
@@ -65,13 +65,13 @@ static void get_ide_dma66(void)
 	/*u32 sm_dev, ide_dev; */
 	struct device *sm_dev, ide_dev;
 
-	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	sm_dev = pcidev_on_root(0x14, 0);
 
 	byte = pci_read_config8(sm_dev, 0xA9);
 	byte |= (1 << 5);	/* Set Gpio9 as input */
 	pci_write_config8(sm_dev, 0xA9, byte);
 
-	ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
+	ide_dev = pcidev_on_root(0x14, 1);
 	byte = pci_read_config8(ide_dev, 0x56);
 	byte &= ~(7 << 0);
 	if ((1 << 5) & pci_read_config8(sm_dev, 0xAA))

src/mainboard/kontron/ktqm77/mainboard.c

@@ -172,7 +172,7 @@ static void mainboard_enable(struct device *dev)
 
 	unsigned disable = 0;
 	if ((get_option(&disable, "ethernet1") == CB_SUCCESS) && disable) {
-		struct device *nic = dev_find_slot(0, PCI_DEVFN(0x1c, 2));
+		struct device *nic = pcidev_on_root(0x1c, 2);
 		if (nic) {
 			printk(BIOS_DEBUG, "DISABLE FIRST NIC!\n");
 			nic->enabled = 0;
@@ -180,7 +180,7 @@ static void mainboard_enable(struct device *dev)
 	}
 	disable = 0;
 	if ((get_option(&disable, "ethernet2") == CB_SUCCESS) && disable) {
-		struct device *nic = dev_find_slot(0, PCI_DEVFN(0x1c, 3));
+		struct device *nic = pcidev_on_root(0x1c, 3);
 		if (nic) {
 			printk(BIOS_DEBUG, "DISABLE SECOND NIC!\n");
 			nic->enabled = 0;

src/mainboard/lenovo/g505s/mptable.c

@@ -142,7 +142,7 @@ static void *smp_write_config_table(void *v)
 	/* on board NIC & Slot PCIE.  */
 
 	/* PCI slots */
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+	struct device *dev = pcidev_on_root(0x14, 4);
 	if (dev && dev->enabled) {
 		u8 bus_pci = dev->link_list->secondary;
 		/* PCI_SLOT 0. */

src/mainboard/lenovo/t400/fadt.c

@@ -22,7 +22,7 @@
 void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 {
 	acpi_header_t *header = &(fadt->header);
-	u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe;
+	u16 pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffe;
 
 	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
 	memcpy(header->signature, "FACP", 4);

src/mainboard/lenovo/t60/mainboard.c

@@ -51,7 +51,7 @@ static void mainboard_init(struct device *dev)
 	if (acpi_is_wakeup_s3())
 		ec_write(0x0c, 0xc7);
 
-	idedev = dev_find_slot(0, PCI_DEVFN(0x1f,1));
+	idedev = pcidev_on_root(0x1f, 1);
 
 	if (!(inb(DEFAULT_GPIOBASE + 0x0c) & 0x40)) {
 		/* legacy I/O connected */

src/mainboard/lenovo/x200/fadt.c

@@ -22,7 +22,7 @@
 void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 {
 	acpi_header_t *header = &(fadt->header);
-	u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe;
+	u16 pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffe;
 
 	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
 	memcpy(header->signature, "FACP", 4);

src/mainboard/lenovo/x201/mainboard.c

@@ -82,7 +82,7 @@ static void mainboard_enable(struct device *dev)
 	dev->ops->init = mainboard_init;
 	dev->ops->acpi_fill_ssdt_generator = fill_ssdt;
 
-	pmbase = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)),
+	pmbase = pci_read_config32(pcidev_on_root(0x1f, 0),
 				   PMBASE) & 0xff80;
 
 	printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase);
@@ -90,9 +90,9 @@ static void mainboard_enable(struct device *dev)
 	outl(0, pmbase + SMI_EN);
 
 	enable_lapic();
-	pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_BASE,
+	pci_write_config32(pcidev_on_root(0x1f, 0), GPIO_BASE,
 			   DEFAULT_GPIOBASE | 1);
-	pci_write_config8(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_CNTL,
+	pci_write_config8(pcidev_on_root(0x1f, 0), GPIO_CNTL,
 			  0x10);
 
 	/* If we're resuming from suspend, blink suspend LED */

src/mainboard/lenovo/x60/mainboard.c

@@ -87,7 +87,7 @@ static void mainboard_init(struct device *dev)
 	if (acpi_is_wakeup_s3())
 		ec_write(0x0c, 0xc7);
 
-	idedev = dev_find_slot(0, PCI_DEVFN(0x1f,1));
+	idedev = pcidev_on_root(0x1f, 1);
 	if (idedev && idedev->chip_info && dock_ultrabay_device_present()) {
 		struct southbridge_intel_i82801gx_config *config = idedev->chip_info;
 		config->ide_enable_primary = 1;

src/mainboard/lenovo/z61t/mainboard.c

@@ -51,7 +51,7 @@ static void mainboard_init(struct device *dev)
 	if (acpi_is_wakeup_s3())
 		ec_write(0x0c, 0xc7);
 
-	idedev = dev_find_slot(0, PCI_DEVFN(0x1f,1));
+	idedev = pcidev_on_root(0x1f, 1);
 
 	if (!(inb(DEFAULT_GPIOBASE + 0x0c) & 0x40)) {
 		/* legacy I/O connected */

src/mainboard/lippert/frontrunner-af/mainboard.c

@@ -97,7 +97,8 @@ static void init(struct device *dev)
 	}
 
 	/* Lower SPI speed from default 66 to 22 MHz for SST 25VF032B */
-	spi_base = (u8*)((uintptr_t)pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x14, 3)), 0xA0) & 0xFFFFFFE0);
+	spi_base = (u8 *)((uintptr_t)pci_read_config32(pcidev_on_root(0x14, 3),
+							   0xA0) & 0xFFFFFFE0);
 	spi_base[0x0D] = (spi_base[0x0D] & ~0x30) | 0x20; // NormSpeed in SPI_Cntrl1 register
 
 	/* Notify the SMC we're alive and kicking, or after a while it will

src/mainboard/lippert/frontrunner-af/mptable.c

@@ -97,7 +97,7 @@ static void *smp_write_config_table(void *v)
 	/* on board NIC & Slot PCIE.	*/
 
 	/* PCI slots */
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+	struct device *dev = pcidev_on_root(0x14, 4);
 	if (dev && dev->enabled) {
 		u8 bus_pci = dev->link_list->secondary;
 		/* PCI_SLOT 0. */

src/mainboard/lippert/toucan-af/mainboard.c

@@ -63,7 +63,8 @@ static void init(struct device *dev)
 	       fch_gpio_state(58)<<2 | fch_gpio_state(57)<<1 | fch_gpio_state(56));
 
 	/* Lower SPI speed from default 66 to 22 MHz for SST 25VF032B */
-	spi_base = (u8*)((uintptr_t)pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x14, 3)), 0xA0) & 0xFFFFFFE0);
+	spi_base = (u8 *)((uintptr_t)pci_read_config32(pcidev_on_root(0x14, 3),
+							   0xA0) & 0xFFFFFFE0);
 	spi_base[0x0D] = (spi_base[0x0D] & ~0x30) | 0x20; // NormSpeed in SPI_Cntrl1 register
 
 	/* Notify the SMC we're alive and kicking, or after a while it will

src/mainboard/lippert/toucan-af/mptable.c

@@ -97,7 +97,7 @@ static void *smp_write_config_table(void *v)
 	/* on board NIC & Slot PCIE.	*/
 
 	/* PCI slots */
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+	struct device *dev = pcidev_on_root(0x14, 4);
 	if (dev && dev->enabled) {
 		u8 bus_pci = dev->link_list->secondary;
 		/* PCI_SLOT 0. */

src/mainboard/msi/ms7721/mptable.c

@@ -142,7 +142,7 @@ static void *smp_write_config_table(void *v)
 	/* on board NIC & Slot PCIE.  */
 
 	/* PCI slots */
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+	struct device *dev = pcidev_on_root(0x14, 4);
 	if (dev && dev->enabled) {
 		u8 bus_pci = dev->link_list->secondary;
 		/* PCI_SLOT 0. */

src/mainboard/packardbell/ms2290/mainboard.c

@@ -99,7 +99,7 @@ static void mainboard_enable(struct device *dev)
 	for (i = 0; i < 256; i++)
 		ec_write (i, dmp[i]);
 
-	pmbase = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)),
+	pmbase = pci_read_config32(pcidev_on_root(0x1f, 0),
 				   PMBASE) & 0xff80;
 
 	printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase);
@@ -107,9 +107,9 @@ static void mainboard_enable(struct device *dev)
 	outl(0, pmbase + SMI_EN);
 
 	enable_lapic();
-	pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_BASE,
+	pci_write_config32(pcidev_on_root(0x1f, 0), GPIO_BASE,
 			   DEFAULT_GPIOBASE | 1);
-	pci_write_config8(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_CNTL,
+	pci_write_config8(pcidev_on_root(0x1f, 0), GPIO_CNTL,
 			  0x10);
 
 	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_LFP, 2);

src/mainboard/pcengines/apu1/mainboard.c

@@ -255,7 +255,7 @@ const char *smbios_mainboard_serial_number(void)
  */
 static void usb_oc_setup(void)
 {
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0x12, 0));
+	struct device *dev = pcidev_on_root(0x12, 0);
 
 	pci_write_config32(dev, 0x58, 0x011f0);
 }

src/mainboard/pcengines/apu2/mainboard.c

@@ -207,7 +207,7 @@ const char *smbios_mainboard_serial_number(void)
 	 * Read secondary bus number from the PCIe bridge where the first NIC is
 	 * connected.
 	 */
-	dev = dev_find_slot(0, PCI_DEVFN(2, 2));
+	dev = pcidev_on_root(2, 2);
 	if ((serial[0] != 0) || !dev)
 		return serial;
 

src/mainboard/roda/rk9/fadt.c

@@ -22,7 +22,7 @@
 void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 {
 	acpi_header_t *header = &(fadt->header);
-	u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe;
+	u16 pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffe;
 
 	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
 	memcpy(header->signature, "FACP", 4);

src/mainboard/siemens/mc_bdx1/mainboard.c

@@ -103,7 +103,7 @@ static void mainboard_enable(struct device *dev)
 static void mainboard_init(void *chip_info)
 {
 	uint8_t actl = 0;
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));
+	struct device *dev = pcidev_on_root(LPC_DEV, LPC_FUNC);
 
 	/* Route SCI to IRQ 10 to free IRQ 9 slot. */
 	actl = pci_read_config8(dev, ACPI_CNTL_OFFSET);
@@ -120,7 +120,7 @@ static void mainboard_final(void *chip_info)
 {
 	void *spi_base = NULL;
 	uint32_t rcba = 0;
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));
+	struct device *dev = pcidev_on_root(LPC_DEV, LPC_FUNC);
 
 	/* Get address of SPI controller. */
 	rcba = (pci_read_config32(dev, 0xf0) & 0xffffc000);

src/mainboard/supermicro/h8scm_fam10/mainboard.c

@@ -36,7 +36,7 @@ void set_pcie_reset(void)
 {
 	struct device *pcie_core_dev;
 
-	pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	pcie_core_dev = pcidev_on_root(0, 0);
 	set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x28282828);
 	set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x000000FF, 0x00000028);
 }
@@ -45,7 +45,7 @@ void set_pcie_dereset(void)
 {
 	struct device *pcie_core_dev;
 
-	pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	pcie_core_dev = pcidev_on_root(0, 0);
 	set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x6F6F6F6F);
 	set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x000000FF, 0x0000006F);
 }

src/northbridge/amd/amdfam10/northbridge.c

@@ -1459,7 +1459,7 @@ static void cpu_bus_scan(struct device *dev)
 	nb_cfg_54 = read_nb_cfg_54();
 
 #if CONFIG_CBB
-	dev_mc = dev_find_slot(0, PCI_DEVFN(CONFIG_CDB, 0)); //0x00
+	dev_mc = pcidev_on_root(CONFIG_CDB, 0); //0x00
 	if (dev_mc && dev_mc->bus) {
 		printk(BIOS_DEBUG, "%s found", dev_path(dev_mc));
 		pci_domain = dev_mc->bus->dev;
@@ -1475,7 +1475,7 @@ static void cpu_bus_scan(struct device *dev)
 	}
 	dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0));
 	if (!dev_mc) {
-		dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0));
+		dev_mc = pcidev_on_root(0x18, 0);
 		if (dev_mc && dev_mc->bus) {
 			printk(BIOS_DEBUG, "%s found\n", dev_path(dev_mc));
 			pci_domain = dev_mc->bus->dev;
@@ -1719,8 +1719,8 @@ static void detect_and_enable_probe_filter(struct device *dev)
 
 		/* Disable L3 and DRAM scrubbers and configure system for probe filter support */
 		for (i = 0; i < sysconf.nodes; i++) {
-			struct device *f2x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 2));
+			struct device *f2x_dev = pcidev_on_root(0x18 + i, 2);
-			struct device *f3x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3));
+			struct device *f3x_dev = pcidev_on_root(0x18 + i, 3);
 
 			f3x58[i] = pci_read_config32(f3x_dev, 0x58);
 			f3x5c[i] = pci_read_config32(f3x_dev, 0x5c);
@@ -1789,7 +1789,7 @@ static void detect_and_enable_probe_filter(struct device *dev)
 
 		/* Enable probe filter */
 		for (i = 0; i < sysconf.nodes; i++) {
-			struct device *f3x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3));
+			struct device *f3x_dev = pcidev_on_root(0x18 + i, 3);
 
 			dword = pci_read_config32(f3x_dev, 0x1c4);
 			dword |= (0x1 << 31);	/* L3TagInit = 1 */
@@ -1810,8 +1810,10 @@ static void detect_and_enable_probe_filter(struct device *dev)
 
 			/* Enable ATM mode */
 			for (i = 0; i < sysconf.nodes; i++) {
-				struct device *f0x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 0));
+				struct device *f0x_dev =
-				struct device *f3x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3));
+						   pcidev_on_root(0x18 + i, 0);
+				struct device *f3x_dev =
+						   pcidev_on_root(0x18 + i, 3);
 
 				dword = pci_read_config32(f0x_dev, 0x68);
 				dword |= (0x1 << 12);	/* ATMModeEn = 1 */
@@ -1827,7 +1829,7 @@ static void detect_and_enable_probe_filter(struct device *dev)
 
 		/* Reenable L3 and DRAM scrubbers */
 		for (i = 0; i < sysconf.nodes; i++) {
-			struct device *f3x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3));
+			struct device *f3x_dev = pcidev_on_root(0x18 + i, 3);
 
 			pci_write_config32(f3x_dev, 0x58, f3x58[i]);
 			pci_write_config32(f3x_dev, 0x5c, f3x5c[i]);
@@ -1863,9 +1865,9 @@ static void detect_and_enable_cache_partitioning(struct device *dev)
 		uint8_t dual_node = 0;
 
 		for (i = 0; i < sysconf.nodes; i++) {
-			struct device *f3x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3));
+			struct device *f3x_dev = pcidev_on_root(0x18 + i, 3);
-			struct device *f4x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 4));
+			struct device *f4x_dev = pcidev_on_root(0x18 + i, 4);
-			struct device *f5x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 5));
+			struct device *f5x_dev = pcidev_on_root(0x18 + i, 5);
 
 			f3xe8 = pci_read_config32(f3x_dev, 0xe8);
 

src/northbridge/amd/amdmct/mct_ddr3/s3utils.c

@@ -80,7 +80,7 @@ static uint32_t read_config32_dct(struct device *dev, uint8_t node, uint8_t dct,
 #ifdef __PRE_RAM__
 		pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1);
 #else
-		struct device *dev_fn1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1));
+		struct device *dev_fn1 = pcidev_on_root(0x18 + node, 1);
 #endif
 
 		/* Select DCT */
@@ -109,7 +109,7 @@ static void write_config32_dct(struct device *dev, uint8_t node, uint8_t dct,
 #ifdef __PRE_RAM__
 		pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1);
 #else
-		struct device *dev_fn1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1));
+		struct device *dev_fn1 = pcidev_on_root(0x18 + node, 1);
 #endif
 
 		/* Select DCT */
@@ -159,7 +159,7 @@ static uint32_t read_amd_dct_index_register_dct(struct device *dev,
 #ifdef __PRE_RAM__
 		pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1);
 #else
-		struct device *dev_fn1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1));
+		struct device *dev_fn1 = pcidev_on_root(0x18 + node, 1);
 #endif
 
 		/* Select DCT */
@@ -280,7 +280,7 @@ static uint32_t read_config32_dct_nbpstate(struct device *dev, uint8_t node,
 					   uint32_t reg)
 {
 	uint32_t dword;
-	struct device *dev_fn1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1));
+	struct device *dev_fn1 = pcidev_on_root(0x18 + node, 1);
 
 	/* Select DCT */
 	dword = pci_read_config32(dev_fn1, 0x10c);
@@ -343,9 +343,9 @@ void copy_mct_data_to_save_variable(struct amd_s3_persistent_data *persistent_da
 
 	/* Load data from DCTs into data structure */
 	for (node = 0; node < MAX_NODES_SUPPORTED; node++) {
-		struct device *dev_fn1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1));
+		struct device *dev_fn1 = pcidev_on_root(0x18 + node, 1);
-		struct device *dev_fn2 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 2));
+		struct device *dev_fn2 = pcidev_on_root(0x18 + node, 2);
-		struct device *dev_fn3 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 3));
+		struct device *dev_fn3 = pcidev_on_root(0x18 + node, 3);
 		/* Test for node presence */
 		if ((!dev_fn1) || (pci_read_config32(dev_fn1, PCI_VENDOR_ID) == 0xffffffff)) {
 			persistent_data->node[node].node_present = 0;

src/northbridge/intel/e7505/northbridge.c

@@ -38,7 +38,7 @@ static void mch_domain_read_resources(struct device *dev)
 
 	pci_domain_read_resources(dev);
 
-	mc_dev = dev_find_slot(0, PCI_DEVFN(0x0, 0));
+	mc_dev = pcidev_on_root(0, 0);
 	if (!mc_dev)
 		die("Could not find MCH device\n");
 

src/northbridge/intel/fsp_rangeley/northbridge.c

@@ -39,7 +39,7 @@ int bridge_silicon_revision(void)
 	if (bridge_revision_id < 0) {
 		uint8_t stepping = cpuid_eax(1) & 0xf;
 		uint8_t bridge_id = pci_read_config16(
-			dev_find_slot(0, PCI_DEVFN(0, 0)),
+			pcidev_on_root(0, 0),
 			PCI_DEVICE_ID) & 0xf0;
 		bridge_revision_id = bridge_id | stepping;
 	}
@@ -62,7 +62,7 @@ static int get_pcie_bar(u32 *base)
 
 	*base = 0;
 
-	dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	dev = pcidev_on_root(0, 0);
 	if (!dev)
 		return 0;
 

src/northbridge/intel/gm45/acpi.c

@@ -68,9 +68,11 @@ unsigned long acpi_fill_mcfg(unsigned long current)
 
 static unsigned long acpi_fill_dmar(unsigned long current)
 {
-	int me_active = (dev_find_slot(0, PCI_DEVFN(3, 0)) != NULL) &&
+	int me_active = (pcidev_on_root(3, 0) != NULL) &&
-		(pci_read_config8(dev_find_slot(0, PCI_DEVFN(3, 0)), PCI_CLASS_REVISION) != 0xff);
+		(pci_read_config8(pcidev_on_root(3, 0), PCI_CLASS_REVISION) !=
-	int stepping = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), PCI_CLASS_REVISION);
+									 0xff);
+	int stepping = pci_read_config8(pcidev_on_root(0, 0),
+							   PCI_CLASS_REVISION);
 
 	unsigned long tmp = current;
 	current += acpi_create_dmar_drhd(current, 0, 0, IOMMU_BASE1);

src/northbridge/intel/gm45/gma.c

@@ -815,7 +815,7 @@ static void gma_set_subsystem(struct device *dev, unsigned int vendor,
 const struct i915_gpu_controller_info *
 intel_gma_get_controller_info(void)
 {
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0x2,0));
+	struct device *dev = pcidev_on_root(0x2, 0);
 	if (!dev) {
 		return NULL;
 	}

src/northbridge/intel/gm45/northbridge.c

@@ -41,7 +41,7 @@ static int decode_pcie_bar(u32 *const base, u32 *const len)
 	*base = 0;
 	*len = 0;
 
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	struct device *dev = pcidev_on_root(0, 0);
 	if (!dev)
 		return 0;
 
@@ -95,7 +95,7 @@ static void mch_domain_read_resources(struct device *dev)
 
 	pci_domain_read_resources(dev);
 
-	struct device *mch = dev_find_slot(0, PCI_DEVFN(0, 0));
+	struct device *mch = pcidev_on_root(0, 0);
 
 	/* Top of Upper Usable DRAM, including remap */
 	touud = pci_read_config16(mch, D0F0_TOUUD);
@@ -196,7 +196,7 @@ static void mch_domain_init(struct device *dev)
 {
 	u32 reg32;
 
-	struct device *mch = dev_find_slot(0, PCI_DEVFN(0, 0));
+	struct device *mch = pcidev_on_root(0, 0);
 
 	/* Enable SERR */
 	reg32 = pci_read_config32(mch, PCI_COMMAND);
@@ -222,7 +222,7 @@ static const char *northbridge_acpi_name(const struct device *dev)
 
 void northbridge_write_smram(u8 smram)
 {
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	struct device *dev = pcidev_on_root(0, 0);
 
 	if (dev == NULL)
 		die("could not find pci 00:00.0!\n");
@@ -309,7 +309,7 @@ static void gm45_init(void *const chip_info)
 		}
 		for (; fn >= 0; --fn) {
 			const struct device *const d =
-				dev_find_slot(0, PCI_DEVFN(dev, fn));
+				pcidev_on_root(dev, fn);
 			if (!d || d->enabled) continue;
 			const u32 deven = pci_read_config32(d0f0, D0F0_DEVEN);
 			pci_write_config32(d0f0, D0F0_DEVEN,

src/northbridge/intel/haswell/acpi.c

@@ -31,7 +31,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
 	int max_buses;
 	u32 mask;
 
-	dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	dev = pcidev_on_root(0, 0);
 	if (!dev)
 		return current;
 
@@ -72,7 +72,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
 
 static unsigned long acpi_fill_dmar(unsigned long current)
 {
-	struct device *const igfx_dev = dev_find_slot(0, PCI_DEVFN(2, 0));
+	struct device *const igfx_dev = pcidev_on_root(2, 0);
 	const u32 gfxvtbar = MCHBAR32(GFXVTBAR) & ~0xfff;
 	const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff;
 	const bool gfxvten = MCHBAR32(GFXVTBAR) & 0x1;

src/northbridge/intel/haswell/gma.c

@@ -512,7 +512,7 @@ static void gma_set_subsystem(struct device *dev, unsigned int vendor,
 const struct i915_gpu_controller_info *
 intel_gma_get_controller_info(void)
 {
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0x2,0));
+	struct device *dev = pcidev_on_root(0x2, 0);
 	if (!dev) {
 		return NULL;
 	}

src/northbridge/intel/haswell/northbridge.c

@@ -449,7 +449,7 @@ static void disable_devices(void)
 		{ PCI_DEVFN(7, 0), DEVEN_D7EN, "\"device 7\"" },
 	};
 
-	struct device *host_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	struct device *host_dev = pcidev_on_root(0x0, 0);
 	u32 deven;
 	size_t i;
 

src/northbridge/intel/i945/acpi.c

@@ -29,7 +29,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
 	u32 pciexbar_reg;
 	int max_buses;
 
-	dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	dev = pcidev_on_root(0, 0);
 	if (!dev)
 		return current;
 

src/northbridge/intel/i945/gma.c

@@ -73,7 +73,7 @@ static int gtt_setup(u8 *mmiobase)
 	/*
 	 * The Video BIOS places the GTT right below top of memory.
 	 */
-	tom = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), TOLUD) << 24;
+	tom = pci_read_config8(pcidev_on_root(0, 0), TOLUD) << 24;
 	PGETBL_save = tom - 256 * KiB;
 	PGETBL_save |= PGETBL_ENABLED;
 	PGETBL_save |= 2; /* set GTT to 256kb */
@@ -357,7 +357,7 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf,
 
 	/* Setup GTT.  */
 
-	reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC);
+	reg16 = pci_read_config16(pcidev_on_root(0, 0), GGC);
 	uma_size = 0;
 	if (!(reg16 & 2)) {
 		uma_size = decode_igd_memory_size((reg16 >> 4) & 7);
@@ -536,7 +536,7 @@ static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf,
 
 	/* Set up GTT.  */
 
-	reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC);
+	reg16 = pci_read_config16(pcidev_on_root(0, 0), GGC);
 	uma_size = 0;
 	if (!(reg16 & 2)) {
 		uma_size = decode_igd_memory_size((reg16 >> 4) & 7);
@@ -725,7 +725,7 @@ static void gma_func0_init(struct device *dev)
    be re-enabled later. */
 static void gma_func0_disable(struct device *dev)
 {
-	struct device *dev_host = dev_find_slot(0, PCI_DEVFN(0x0, 0));
+	struct device *dev_host = pcidev_on_root(0x0, 0);
 
 	pci_write_config16(dev, GCFC, 0xa00);
 	pci_write_config16(dev_host, GGC, (1 << 1));
@@ -768,7 +768,7 @@ static void gma_set_subsystem(struct device *dev, unsigned int vendor,
 const struct i915_gpu_controller_info *
 intel_gma_get_controller_info(void)
 {
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0x2, 0));
+	struct device *dev = pcidev_on_root(0x2, 0);
 	if (!dev)
 		return NULL;
 	struct northbridge_intel_i945_config *chip = dev->chip_info;

src/northbridge/intel/i945/northbridge.c

@@ -34,7 +34,7 @@ static int get_pcie_bar(u32 *base)
 
 	*base = 0;
 
-	dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	dev = pcidev_on_root(0, 0);
 	if (!dev)
 		return 0;
 
@@ -76,16 +76,16 @@ static void mch_domain_read_resources(struct device *dev)
 	printk(BIOS_DEBUG, "pci_tolm: 0x%x\n", pci_tolm);
 
 	printk(BIOS_SPEW, "Base of stolen memory: 0x%08x\n",
-		    pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), BSM));
+		    pci_read_config32(pcidev_on_root(2, 0), BSM));
 
-	tolud = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), TOLUD);
+	tolud = pci_read_config8(pcidev_on_root(0, 0), TOLUD);
 	printk(BIOS_SPEW, "Top of Low Used DRAM: 0x%08x\n", tolud << 24);
 
 	tomk = tolud << 14;
 	tomk_stolen = tomk;
 
 	/* Note: subtract IGD device and TSEG */
-	reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC);
+	reg16 = pci_read_config16(pcidev_on_root(0, 0), GGC);
 	if (!(reg16 & 2)) {
 		printk(BIOS_DEBUG, "IGD decoded, subtracting ");
 		int uma_size = decode_igd_memory_size((reg16 >> 4) & 7);
@@ -98,8 +98,8 @@ static void mch_domain_read_resources(struct device *dev)
 		uma_memory_size = uma_size * 1024ULL;
 	}
 
-	tseg_sizek = decode_tseg_size(pci_read_config8(dev_find_slot(0,
+	tseg_sizek = decode_tseg_size(pci_read_config8(pcidev_on_root(0, 0),
-					PCI_DEVFN(0, 0)), ESMRAMC)) >> 10;
+							ESMRAMC)) >> 10;
 	printk(BIOS_DEBUG, "TSEG decoded, subtracting %dM\n", tseg_sizek >> 10);
 	tomk_stolen -= tseg_sizek;
 	tseg_memory_base = tomk_stolen * 1024ULL;
@@ -157,7 +157,7 @@ static const char *northbridge_acpi_name(const struct device *dev)
 
 void northbridge_write_smram(u8 smram)
 {
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	struct device *dev = pcidev_on_root(0, 0);
 
 	if (dev == NULL)
 		die("could not find pci 00:00.0!\n");

src/northbridge/intel/i945/raminit.c

@@ -1219,7 +1219,7 @@ static int sdram_program_row_boundaries(struct sys_info *sysinfo)
 	tom = tolud >> 3;
 
 	/* Limit the value of TOLUD to leave some space for PCI memory. */
-	dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	dev = pcidev_on_root(0, 0);
 	if (dev)
 		cfg = dev->chip_info;
 

src/northbridge/intel/nehalem/gma.c

@@ -658,7 +658,7 @@ static void gma_read_resources(struct device *dev)
 const struct i915_gpu_controller_info *
 intel_gma_get_controller_info(void)
 {
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0x2,0));
+	struct device *dev = pcidev_on_root(0x2, 0);
 	if (!dev) {
 		return NULL;
 	}

src/northbridge/intel/nehalem/northbridge.c

@@ -39,7 +39,7 @@ int bridge_silicon_revision(void)
 	if (bridge_revision_id < 0) {
 		uint8_t stepping = cpuid_eax(1) & 0xf;
 		uint8_t bridge_id =
-		    pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)),
+		    pci_read_config16(pcidev_on_root(0, 0),
 				      PCI_DEVICE_ID) & 0xf0;
 		bridge_revision_id = bridge_id | stepping;
 	}
@@ -129,8 +129,8 @@ static void mc_read_resources(struct device *dev)
 
 	mmconf_resource(dev, 0x50);
 
-	tseg_base = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), TSEG);
+	tseg_base = pci_read_config32(pcidev_on_root(0, 0), TSEG);
-	TOUUD = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)),
+	TOUUD = pci_read_config16(pcidev_on_root(0, 0),
 				  D0F0_TOUUD);
 
 	printk(BIOS_DEBUG, "ram_before_4g_top: 0x%x\n", tseg_base);
@@ -142,7 +142,7 @@ static void mc_read_resources(struct device *dev)
 
 	mmio_resource(dev, 5, tseg_base >> 10, CONFIG_SMM_TSEG_SIZE >> 10);
 
-	reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), D0F0_GGC);
+	reg16 = pci_read_config16(pcidev_on_root(0, 0), D0F0_GGC);
 	const int uma_sizes_gtt[16] =
 	    { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4, 42, 42, 42, 42 };
 	/* Igd memory */
@@ -156,9 +156,9 @@ static void mc_read_resources(struct device *dev)
 	uma_size_gtt = uma_sizes_gtt[(reg16 >> 8) & 0xF];
 
 	igd_base =
-	    pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), D0F0_IGD_BASE);
+	    pci_read_config32(pcidev_on_root(0, 0), D0F0_IGD_BASE);
 	gtt_base =
-	    pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), D0F0_GTT_BASE);
+	    pci_read_config32(pcidev_on_root(0, 0), D0F0_GTT_BASE);
 	mmio_resource(dev, 6, gtt_base >> 10, uma_size_gtt << 10);
 	mmio_resource(dev, 7, igd_base >> 10, uma_size_igd << 10);
 
@@ -174,7 +174,7 @@ static void mc_read_resources(struct device *dev)
 
 u32 northbridge_get_tseg_base(void)
 {
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	struct device *dev = pcidev_on_root(0, 0);
 
 	return pci_read_config32(dev, TSEG) & ~1;
 }

src/northbridge/intel/pineview/early_init.c

@@ -41,7 +41,7 @@ static void early_graphics_setup(void)
 	u16 reg16;
 	u32 reg32;
 
-	const struct device *d0f0 = dev_find_slot(0, PCI_DEVFN(0,0));
+	const struct device *d0f0 = pcidev_on_root(0, 0);
 	const struct northbridge_intel_pineview_config *config = d0f0->chip_info;
 
 	pci_write_config8(D0F0, DEVEN, BOARD_DEVEN);

src/northbridge/intel/pineview/gma.c

@@ -72,7 +72,7 @@ void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb)
 static int gtt_setup(u8 *mmiobase)
 {
 	u32 gttbase;
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0,0));
+	struct device *dev = pcidev_on_root(0, 0);
 
 	gttbase = pci_read_config32(dev, BGSM);
 	printk(BIOS_DEBUG, "gttbase = %08x\n", gttbase);
@@ -319,7 +319,7 @@ static void gma_set_subsystem(struct device *dev, unsigned int vendor,
 
 const struct i915_gpu_controller_info *intel_gma_get_controller_info(void)
 {
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0x2,0));
+	struct device *dev = pcidev_on_root(0x2, 0);
 	if (!dev) {
 		printk(BIOS_WARNING, "WARNING: Can't find IGD (0,2,0)\n");
 		return NULL;

src/northbridge/intel/pineview/northbridge.c

@@ -60,7 +60,7 @@ static void mch_domain_read_resources(struct device *dev)
 	u16 index;
 	const u32 top32memk = 4 * (GiB / KiB);
 
-	struct device *mch = dev_find_slot(0, PCI_DEVFN(0, 0));
+	struct device *mch = pcidev_on_root(0, 0);
 
 	index = 3;
 
@@ -143,7 +143,7 @@ static void mch_domain_read_resources(struct device *dev)
 
 void northbridge_write_smram(u8 smram)
 {
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	struct device *dev = pcidev_on_root(0, 0);
 
 	if (dev == NULL)
 		die("could not find pci 00:00.0!\n");

src/northbridge/intel/sandybridge/acpi.c

@@ -29,7 +29,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
 	u32 pciexbar_reg;
 	int max_buses;
 
-	struct device *const dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	struct device *const dev = pcidev_on_root(0, 0);
 
 	if (!dev)
 		return current;
@@ -68,7 +68,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
 
 static unsigned long acpi_fill_dmar(unsigned long current)
 {
-	const struct device *const igfx = dev_find_slot(0, PCI_DEVFN(2, 0));
+	const struct device *const igfx = pcidev_on_root(2, 0);
 
 	if (igfx && igfx->enabled) {
 		const unsigned long tmp = current;

src/northbridge/intel/sandybridge/gma.c

@@ -684,7 +684,7 @@ static void gma_set_subsystem(struct device *dev, unsigned int vendor,
 const struct i915_gpu_controller_info *
 intel_gma_get_controller_info(void)
 {
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0x2,0));
+	struct device *dev = pcidev_on_root(0x2, 0);
 	if (!dev) {
 		return NULL;
 	}
@@ -737,7 +737,7 @@ static const char *gma_acpi_name(const struct device *dev)
 static void gma_func0_disable(struct device *dev)
 {
 	u16 reg16;
-	struct device *dev_host = dev_find_slot(0, PCI_DEVFN(0,0));
+	struct device *dev_host = pcidev_on_root(0, 0);
 
 	reg16 = pci_read_config16(dev_host, GGC);
 	reg16 |= (1 << 1); /* disable VGA decode */

src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c

@@ -504,7 +504,7 @@ int i915lightup_ivy(const struct i915_gpu_controller_info *info,
 	write32(mmio + 0x0004f05c, 0x00000008);
 
 	/* Linux relies on VBT for panel info.  */
-	generate_fake_intel_oprom(info, dev_find_slot(0, PCI_DEVFN(2, 0)),
+	generate_fake_intel_oprom(info, pcidev_on_root(2, 0),
 				  "$VBT SNB/IVB-MOBILE");
 
 	return 1;

src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c

@@ -469,7 +469,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
 	}
 
 	/* Linux relies on VBT for panel info.  */
-	generate_fake_intel_oprom(info, dev_find_slot(0, PCI_DEVFN(2, 0)),
+	generate_fake_intel_oprom(info, pcidev_on_root(2, 0),
 				  "$VBT SNB/IVB-MOBILE");
 
 	return 1;

src/northbridge/intel/sandybridge/iommu.c

@@ -37,8 +37,7 @@ void sandybridge_init_iommu(void)
 	/* lock policies */
 	write32((void *)(IOMMU_BASE1 + 0xff0), 0x80000000);
 
-	const struct device *const azalia =
+	const struct device *const azalia = pcidev_on_root(0x1b, 0);
-		dev_find_slot(0x00, PCI_DEVFN(0x1b, 0));
 	if (azalia && azalia->enabled) {
 		write32((void *)(IOMMU_BASE2 + 0xff0), 0x20000000);
 		write32((void *)(IOMMU_BASE2 + 0xff0), 0xa0000000);

src/northbridge/intel/sandybridge/northbridge.c

@@ -42,7 +42,7 @@ int bridge_silicon_revision(void)
 	if (bridge_revision_id < 0) {
 		uint8_t stepping = cpuid_eax(1) & 0xf;
 		uint8_t bridge_id = pci_read_config16(
-			dev_find_slot(0, PCI_DEVFN(0, 0)),
+			pcidev_on_root(0, 0),
 			PCI_DEVICE_ID) & 0xf0;
 		bridge_revision_id = bridge_id | stepping;
 	}
@@ -65,7 +65,7 @@ static int get_pcie_bar(u32 *base)
 
 	*base = 0;
 
-	dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	dev = pcidev_on_root(0, 0);
 	if (!dev)
 		return 0;
 
@@ -151,7 +151,7 @@ static void pci_domain_set_resources(struct device *dev)
 	 * 14fe00000   5368MB TOUUD
 	 */
 
-	struct device *mch = dev_find_slot(0, PCI_DEVFN(0, 0));
+	struct device *mch = pcidev_on_root(0, 0);
 
 	/* Top of Upper Usable DRAM, including remap */
 	touud = pci_read_config32(mch, TOUUD+4);
@@ -351,46 +351,46 @@ static void disable_peg(void)
 	struct device *dev;
 	u32 reg;
 
-	dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	dev = pcidev_on_root(0, 0);
 	reg = pci_read_config32(dev, DEVEN);
 
-	dev = dev_find_slot(0, PCI_DEVFN(1, 2));
+	dev = pcidev_on_root(1, 2);
 	if (!dev || !dev->enabled) {
 		printk(BIOS_DEBUG, "Disabling PEG12.\n");
 		reg &= ~DEVEN_PEG12;
 	}
-	dev = dev_find_slot(0, PCI_DEVFN(1, 1));
+	dev = pcidev_on_root(1, 1);
 	if (!dev || !dev->enabled) {
 		printk(BIOS_DEBUG, "Disabling PEG11.\n");
 		reg &= ~DEVEN_PEG11;
 	}
-	dev = dev_find_slot(0, PCI_DEVFN(1, 0));
+	dev = pcidev_on_root(1, 0);
 	if (!dev || !dev->enabled) {
 		printk(BIOS_DEBUG, "Disabling PEG10.\n");
 		reg &= ~DEVEN_PEG10;
 	}
-	dev = dev_find_slot(0, PCI_DEVFN(2, 0));
+	dev = pcidev_on_root(2, 0);
 	if (!dev || !dev->enabled) {
 		printk(BIOS_DEBUG, "Disabling IGD.\n");
 		reg &= ~DEVEN_IGD;
 	}
-	dev = dev_find_slot(0, PCI_DEVFN(4, 0));
+	dev = pcidev_on_root(4, 0);
 	if (!dev || !dev->enabled) {
 		printk(BIOS_DEBUG, "Disabling Device 4.\n");
 		reg &= ~DEVEN_D4EN;
 	}
-	dev = dev_find_slot(0, PCI_DEVFN(6, 0));
+	dev = pcidev_on_root(6, 0);
 	if (!dev || !dev->enabled) {
 		printk(BIOS_DEBUG, "Disabling PEG60.\n");
 		reg &= ~DEVEN_PEG60;
 	}
-	dev = dev_find_slot(0, PCI_DEVFN(7, 0));
+	dev = pcidev_on_root(7, 0);
 	if (!dev || !dev->enabled) {
 		printk(BIOS_DEBUG, "Disabling Device 7.\n");
 		reg &= ~DEVEN_D7EN;
 	}
 
-	dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	dev = pcidev_on_root(0, 0);
 	pci_write_config32(dev, DEVEN, reg);
 	if (!(reg & (DEVEN_PEG60 | DEVEN_PEG10 | DEVEN_PEG11 | DEVEN_PEG12))) {
 		/* Set the PEG clock gating bit.
@@ -469,7 +469,7 @@ static u32 northbridge_get_base_reg(struct device *dev, int reg)
 
 u32 northbridge_get_tseg_base(void)
 {
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	struct device *dev = pcidev_on_root(0, 0);
 
 	return northbridge_get_base_reg(dev, TSEG);
 }
@@ -481,7 +481,7 @@ u32 northbridge_get_tseg_size(void)
 
 void northbridge_write_smram(u8 smram)
 {
-	pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, smram);
+	pci_write_config8(pcidev_on_root(0, 0), SMRAM, smram);
 }
 
 static struct pci_operations intel_pci_ops = {

src/northbridge/intel/x4x/acpi.c

@@ -30,7 +30,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
 	u32 pciexbar = 0;
 	u32 length = 0;
 
-	dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	dev = pcidev_on_root(0, 0);
 	if (!decode_pciebar(&pciexbar, &length))
 		return current;
 

src/northbridge/intel/x4x/gma.c

@@ -69,10 +69,10 @@ static void gma_func0_init(struct device *dev)
 	pci_write_config32(dev, PCI_COMMAND, reg32);
 
 	/* configure GMBUSFREQ */
-	reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x2, 0)), 0xcc);
+	reg16 = pci_read_config16(pcidev_on_root(0x2, 0), 0xcc);
 	reg16 &= ~0x1ff;
 	reg16 |= 0xbc;
-	pci_write_config16(dev_find_slot(0, PCI_DEVFN(0x2, 0)), 0xcc, reg16);
+	pci_write_config16(pcidev_on_root(0x2, 0), 0xcc, reg16);
 
 	int vga_disable = (pci_read_config16(dev, D0F0_GGC) & 2) >> 1;
 
@@ -93,7 +93,7 @@ static void gma_func0_init(struct device *dev)
 
 static void gma_func0_disable(struct device *dev)
 {
-	struct device *dev_host = dev_find_slot(0, PCI_DEVFN(0, 0));
+	struct device *dev_host = pcidev_on_root(0, 0);
 	u16 ggc;
 
 	ggc = pci_read_config16(dev_host, D0F0_GGC);
@@ -117,7 +117,7 @@ static void gma_set_subsystem(struct device *dev, unsigned int vendor,
 const struct i915_gpu_controller_info *
 intel_gma_get_controller_info(void)
 {
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0x2, 0));
+	struct device *dev = pcidev_on_root(0x2, 0);
 	if (!dev)
 		return NULL;
 	struct northbridge_intel_x4x_config *chip = dev->chip_info;