Update the k8 code for the v3 resource allocator.
The major change is that the K8 registers don't get touched until the end of resource allocation. Fam10 code could be updated the same way. Move VGA code before resource allocation but after device enumeration. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4395 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Myles Watson
parent
29cc9eda20
commit
c7233e0899
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@ -663,9 +663,9 @@ static void avoid_fixed_resources(struct device *dev)
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#if CONFIG_CONSOLE_VGA == 1
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device_t vga_pri = 0;
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static void allocate_vga_resource(void)
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static void set_vga_bridge_bits(void)
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{
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#warning "FIXME modify allocate_vga_resource so it is less pci centric!"
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#warning "FIXME modify set_vga_bridge so it is less pci centric!"
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#warning "This function knows too much about PCI stuff, it should be just a iterator/visitor."
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/* FIXME: Handle the VGA palette snooping. */
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@ -716,7 +716,7 @@ static void allocate_vga_resource(void)
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if (vga) {
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/* VGA is first add on card or the only onboard VGA. */
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printk_debug("Allocating VGA resource %s\n", dev_path(vga));
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printk_debug("Setting up VGA for %s\n", dev_path(vga));
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/* All legacy VGA cards have MEM & I/O space registers. */
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vga->command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
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vga_pri = vga;
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@ -921,6 +921,10 @@ void dev_configure(void)
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struct device *child;
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int i;
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#if CONFIG_CONSOLE_VGA == 1
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set_vga_bridge_bits();
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#endif
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printk_info("Allocating resources...\n");
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root = &dev_root;
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@ -984,12 +988,6 @@ void dev_configure(void)
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}
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}
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#if CONFIG_CONSOLE_VGA == 1
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/* Allocate the VGA I/O resource. */
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allocate_vga_resource();
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print_resource_tree(root, BIOS_DEBUG, "After VGA.");
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#endif
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/* Store the computed resource allocations into device registers ... */
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printk_info("Setting resources...\n");
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for (child = root->link[0].children; child; child = child->sibling) {
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@ -36,56 +36,38 @@
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struct amdk8_sysconf_t sysconf;
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#define FX_DEVS 8
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static device_t __f0_dev[FX_DEVS];
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static device_t __f1_dev[FX_DEVS];
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#if 0
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static void debug_fx_devs(void)
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{
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int i;
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for(i = 0; i < FX_DEVS; i++) {
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device_t dev;
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dev = __f0_dev[i];
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if (dev) {
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printk_debug("__f0_dev[%d]: %s bus: %p\n",
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i, dev_path(dev), dev->bus);
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}
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dev = __f1_dev[i];
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if (dev) {
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printk_debug("__f1_dev[%d]: %s bus: %p\n",
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i, dev_path(dev), dev->bus);
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}
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}
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}
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#endif
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#define MAX_FX_DEVS 8
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static device_t __f0_dev[MAX_FX_DEVS];
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static device_t __f1_dev[MAX_FX_DEVS];
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static unsigned fx_devs=0;
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static void get_fx_devs(void)
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{
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int i;
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if (__f1_dev[0]) {
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return;
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}
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for(i = 0; i < FX_DEVS; i++) {
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for(i = 0; i < MAX_FX_DEVS; i++) {
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__f0_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 0));
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__f1_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 1));
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if (__f0_dev[i] != NULL && __f1_dev[i] != NULL)
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fx_devs = i+1;
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}
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if (!__f1_dev[0]) {
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die("Cannot find 0:0x18.1\n");
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if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) {
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die("Cannot find 0:0x18.[0|1]\n");
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}
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}
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static uint32_t f1_read_config32(unsigned reg)
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{
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get_fx_devs();
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if ( fx_devs == 0)
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get_fx_devs();
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return pci_read_config32(__f1_dev[0], reg);
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}
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static void f1_write_config32(unsigned reg, uint32_t value)
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{
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int i;
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get_fx_devs();
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for(i = 0; i < FX_DEVS; i++) {
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if ( fx_devs == 0)
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get_fx_devs();
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for(i = 0; i < fx_devs; i++) {
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device_t dev;
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dev = __f1_dev[i];
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if (dev && dev->enabled) {
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@ -291,7 +273,7 @@ static int reg_useable(unsigned reg,
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unsigned nodeid, link=0;
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int result;
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res = 0;
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for(nodeid = 0; !res && (nodeid < FX_DEVS); nodeid++) {
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for(nodeid = 0; !res && (nodeid < fx_devs); nodeid++) {
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device_t dev;
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dev = __f0_dev[nodeid];
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if (!dev)
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@ -313,13 +295,14 @@ static int reg_useable(unsigned reg,
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return result;
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}
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static struct resource *amdk8_find_iopair(device_t dev, unsigned nodeid, unsigned link)
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static unsigned amdk8_find_reg(device_t dev, unsigned nodeid, unsigned link,
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unsigned min, unsigned max)
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{
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struct resource *resource;
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unsigned resource;
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unsigned free_reg, reg;
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resource = 0;
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free_reg = 0;
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for(reg = 0xc0; reg <= 0xd8; reg += 0x8) {
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for(reg = min; reg <= max; reg += 0x8) {
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int result;
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result = reg_useable(reg, dev, nodeid, link);
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if (result == 1) {
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@ -331,40 +314,23 @@ static struct resource *amdk8_find_iopair(device_t dev, unsigned nodeid, unsigne
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free_reg = reg;
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}
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}
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if (reg > 0xd8) {
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if (reg > max) {
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reg = free_reg;
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}
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if (reg > 0) {
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resource = new_resource(dev, IOINDEX(0x100 + reg, link));
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resource = IOINDEX(0x100 + reg, link);
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}
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return resource;
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}
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static struct resource *amdk8_find_mempair(device_t dev, unsigned nodeid, unsigned link)
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static unsigned amdk8_find_iopair(device_t dev, unsigned nodeid, unsigned link)
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{
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struct resource *resource;
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unsigned free_reg, reg;
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resource = 0;
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free_reg = 0;
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for(reg = 0x80; reg <= 0xb8; reg += 0x8) {
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int result;
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result = reg_useable(reg, dev, nodeid, link);
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if (result == 1) {
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/* I have been allocated this one */
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break;
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}
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else if (result > 1) {
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/* I have a free register pair */
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free_reg = reg;
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}
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}
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if (reg > 0xb8) {
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reg = free_reg;
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}
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if (reg > 0) {
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resource = new_resource(dev, IOINDEX(0x100 + reg, link));
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}
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return resource;
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return amdk8_find_reg(dev, nodeid, link, 0xc0, 0xd8);
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}
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static unsigned amdk8_find_mempair(device_t dev, unsigned nodeid, unsigned link)
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{
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return amdk8_find_reg(dev, nodeid, link, 0x80, 0xb8);
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}
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static void amdk8_link_read_bases(device_t dev, unsigned nodeid, unsigned link)
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@ -372,7 +338,7 @@ static void amdk8_link_read_bases(device_t dev, unsigned nodeid, unsigned link)
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struct resource *resource;
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/* Initialize the io space constraints on the current bus */
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resource = amdk8_find_iopair(dev, nodeid, link);
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resource = new_resource(dev, IOINDEX(0, link));
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if (resource) {
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resource->base = 0;
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resource->size = 0;
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@ -383,7 +349,7 @@ static void amdk8_link_read_bases(device_t dev, unsigned nodeid, unsigned link)
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}
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/* Initialize the prefetchable memory constraints on the current bus */
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resource = amdk8_find_mempair(dev, nodeid, link);
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resource = new_resource(dev, IOINDEX(2, link));
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if (resource) {
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resource->base = 0;
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resource->size = 0;
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@ -397,7 +363,7 @@ static void amdk8_link_read_bases(device_t dev, unsigned nodeid, unsigned link)
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}
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/* Initialize the memory constraints on the current bus */
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resource = amdk8_find_mempair(dev, nodeid, link);
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resource = new_resource(dev, IOINDEX(1, link));
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if (resource) {
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resource->base = 0;
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resource->size = 0;
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@ -408,6 +374,8 @@ static void amdk8_link_read_bases(device_t dev, unsigned nodeid, unsigned link)
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}
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}
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static void amdk8_create_vga_resource(device_t dev, unsigned nodeid);
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static void amdk8_read_resources(device_t dev)
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{
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unsigned nodeid, link;
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@ -417,6 +385,8 @@ static void amdk8_read_resources(device_t dev)
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amdk8_link_read_bases(dev, nodeid, link);
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}
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}
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amdk8_create_vga_resource(dev, nodeid);
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}
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static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned nodeid)
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@ -518,8 +488,6 @@ static void amdk8_create_vga_resource(device_t dev, unsigned nodeid)
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{
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struct resource *resource;
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unsigned link;
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uint32_t base, limit;
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unsigned reg;
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/* find out which link the VGA card is connected,
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* we only deal with the 'first' vga card */
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@ -543,31 +511,17 @@ static void amdk8_create_vga_resource(device_t dev, unsigned nodeid)
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printk_debug("VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link);
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/* allocate a temp resrouce for legacy VGA buffer */
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resource = amdk8_find_mempair(dev, nodeid, link);
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/* allocate a temp resource for the legacy VGA buffer */
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resource = new_resource(dev, IOINDEX(4, link));
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if(!resource){
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printk_debug("VGA: Can not find free mmio reg for legacy VGA buffer\n");
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printk_debug("VGA: %s out of resources.\n", dev_path(dev));
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return;
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}
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resource->base = 0xa0000;
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resource->size = 0x20000;
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/* write the resource to the hardware */
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reg = resource->index & 0xfc;
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base = f1_read_config32(reg);
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limit = f1_read_config32(reg + 0x4);
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base &= 0x000000f0;
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base |= (resource->base >> 8) & 0xffffff00;
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base |= 3;
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limit &= 0x00000048;
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limit |= (resource_end(resource) >> 8) & 0xffffff00;
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limit |= (resource->index & 3) << 4;
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limit |= (nodeid & 7);
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f1_write_config32(reg + 0x4, limit);
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f1_write_config32(reg, base);
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/* release the temp resource */
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resource->flags = 0;
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resource->limit = 0xffffffff;
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resource->flags = IORESOURCE_FIXED | IORESOURCE_MEM |
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IORESOURCE_ASSIGNED;
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}
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static void amdk8_set_resources(device_t dev)
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@ -578,13 +532,36 @@ static void amdk8_set_resources(device_t dev)
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/* Find the nodeid */
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nodeid = amdk8_nodeid(dev);
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amdk8_create_vga_resource(dev, nodeid);
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/* Set each resource we have found */
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for(i = 0; i < dev->resources; i++) {
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amdk8_set_resource(dev, &dev->resource[i], nodeid);
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struct resource *res = &dev->resource[i];
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struct resource *old = NULL;
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unsigned index;
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if (res->size == 0) /* No need to allocate registers. */
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continue;
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if (res->flags & IORESOURCE_IO)
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index = amdk8_find_iopair(dev, nodeid,
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IOINDEX_LINK(res->index));
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else
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index = amdk8_find_mempair(dev, nodeid,
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IOINDEX_LINK(res->index));
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old = probe_resource(dev, index);
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if (old) {
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res->index = old->index;
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old->index = 0;
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old->flags = 0;
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}
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else
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res->index = index;
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amdk8_set_resource(dev, res, nodeid);
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}
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compact_resources(dev);
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for(link = 0; link < dev->links; link++) {
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struct bus *bus;
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bus = &dev->link[link];
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@ -634,7 +611,6 @@ struct chip_operations northbridge_amd_amdk8_ops = {
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static void amdk8_domain_read_resources(device_t dev)
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{
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struct resource *resource;
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unsigned reg;
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/* Find the already assigned resource pairs */
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@ -652,10 +628,12 @@ static void amdk8_domain_read_resources(device_t dev)
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reg_dev = __f0_dev[nodeid];
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if (reg_dev) {
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/* Reserve the resource */
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struct resource *reg_resource;
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reg_resource = new_resource(reg_dev, IOINDEX(0x100 + reg, link));
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if (reg_resource) {
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reg_resource->flags = 1;
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struct resource *res;
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res = new_resource(reg_dev, IOINDEX(0x100 + reg, link));
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if (res) {
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res->base = base;
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res->limit = limit;
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res->flags = 1;
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}
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}
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}
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@ -691,7 +669,8 @@ static void tolm_test(void *gp, struct device *dev, struct resource *new)
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struct resource **best_p = gp;
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struct resource *best;
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best = *best_p;
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if (!best || (best->base > new->base)) {
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/* Skip VGA. */
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if (!best || (best->base > new->base && new->base > 0xa0000)) {
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best = new;
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}
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*best_p = best;
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@ -725,15 +704,14 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
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mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK;
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mem_hole.node_id = -1;
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for (i = 0; i < FX_DEVS; i++) {
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for (i = 0; i < fx_devs; i++) {
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uint32_t base;
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uint32_t hole;
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base = f1_read_config32(0x40 + (i << 3));
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if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
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continue;
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}
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if (!__f1_dev[i])
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continue;
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hole = pci_read_config32(__f1_dev[i], 0xf0);
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if(hole & 1) { // we find the hole
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mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;
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@ -769,9 +747,10 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
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return mem_hole;
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}
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static void disable_hoist_memory(unsigned long hole_startk, int i)
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static void disable_hoist_memory(unsigned long hole_startk, int node_id)
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{
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int ii;
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int i;
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device_t dev;
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uint32_t base, limit;
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uint32_t hoist;
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@ -787,33 +766,35 @@ static void disable_hoist_memory(unsigned long hole_startk, int i)
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hole_sizek = (4*1024*1024) - hole_startk;
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for(ii=7;ii>i;ii--) {
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for(i=7;i>node_id;i--) {
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base = f1_read_config32(0x40 + (ii << 3));
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base = f1_read_config32(0x40 + (i << 3));
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if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
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continue;
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}
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limit = f1_read_config32(0x44 + (ii << 3));
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f1_write_config32(0x44 + (ii << 3),limit - (hole_sizek << 2));
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f1_write_config32(0x40 + (ii << 3),base - (hole_sizek << 2));
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limit = f1_read_config32(0x44 + (i << 3));
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f1_write_config32(0x44 + (i << 3),limit - (hole_sizek << 2));
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f1_write_config32(0x40 + (i << 3),base - (hole_sizek << 2));
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}
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limit = f1_read_config32(0x44 + (i << 3));
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f1_write_config32(0x44 + (i << 3),limit - (hole_sizek << 2));
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dev = __f1_dev[i];
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if (dev) {
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hoist = pci_read_config32(dev, 0xf0);
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if(hoist & 1) {
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pci_write_config32(dev, 0xf0, 0);
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} else {
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base = pci_read_config32(dev, 0x40 + (i << 3));
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f1_write_config32(0x40 + (i << 3),base - (hole_sizek << 2));
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}
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limit = f1_read_config32(0x44 + (node_id << 3));
|
||||
f1_write_config32(0x44 + (node_id << 3),limit - (hole_sizek << 2));
|
||||
dev = __f1_dev[node_id];
|
||||
if (dev == NULL) {
|
||||
printk_err("%s: node %x is NULL!\n", __func__, node_id);
|
||||
return;
|
||||
}
|
||||
hoist = pci_read_config32(dev, 0xf0);
|
||||
if(hoist & 1)
|
||||
pci_write_config32(dev, 0xf0, 0);
|
||||
else {
|
||||
base = pci_read_config32(dev, 0x40 + (node_id << 3));
|
||||
f1_write_config32(0x40 + (node_id << 3),base - (hole_sizek << 2));
|
||||
}
|
||||
}
|
||||
|
||||
static uint32_t hoist_memory(unsigned long hole_startk, int i)
|
||||
static uint32_t hoist_memory(unsigned long hole_startk, int node_id)
|
||||
{
|
||||
int ii;
|
||||
int i;
|
||||
uint32_t carry_over;
|
||||
device_t dev;
|
||||
uint32_t base, limit;
|
||||
|
|
@ -822,27 +803,27 @@ static uint32_t hoist_memory(unsigned long hole_startk, int i)
|
|||
|
||||
carry_over = (4*1024*1024) - hole_startk;
|
||||
|
||||
for(ii=7;ii>i;ii--) {
|
||||
for(i=7;i>node_id;i--) {
|
||||
|
||||
base = f1_read_config32(0x40 + (ii << 3));
|
||||
base = f1_read_config32(0x40 + (i << 3));
|
||||
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
|
||||
continue;
|
||||
}
|
||||
limit = f1_read_config32(0x44 + (ii << 3));
|
||||
f1_write_config32(0x44 + (ii << 3),limit + (carry_over << 2));
|
||||
f1_write_config32(0x40 + (ii << 3),base + (carry_over << 2));
|
||||
limit = f1_read_config32(0x44 + (i << 3));
|
||||
f1_write_config32(0x44 + (i << 3),limit + (carry_over << 2));
|
||||
f1_write_config32(0x40 + (i << 3),base + (carry_over << 2));
|
||||
}
|
||||
limit = f1_read_config32(0x44 + (i << 3));
|
||||
f1_write_config32(0x44 + (i << 3),limit + (carry_over << 2));
|
||||
dev = __f1_dev[i];
|
||||
base = pci_read_config32(dev, 0x40 + (i << 3));
|
||||
limit = f1_read_config32(0x44 + (node_id << 3));
|
||||
f1_write_config32(0x44 + (node_id << 3),limit + (carry_over << 2));
|
||||
dev = __f1_dev[node_id];
|
||||
base = pci_read_config32(dev, 0x40 + (node_id << 3));
|
||||
basek = (base & 0xffff0000) >> 2;
|
||||
if(basek == hole_startk) {
|
||||
//don't need set memhole here, because hole off set will be 0, overflow
|
||||
//so need to change base reg instead, new basek will be 4*1024*1024
|
||||
base &= 0x0000ffff;
|
||||
base |= (4*1024*1024)<<2;
|
||||
f1_write_config32(0x40 + (i<<3), base);
|
||||
f1_write_config32(0x40 + (node_id<<3), base);
|
||||
}
|
||||
else if (dev)
|
||||
{
|
||||
|
|
@ -980,7 +961,7 @@ static void amdk8_domain_set_resources(device_t dev)
|
|||
#if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1
|
||||
//We need to double check if the mmio_basek is valid for hole setting, if it is equal to basek, we need to decrease it some
|
||||
uint32_t basek_pri;
|
||||
for (i = 0; i < FX_DEVS; i++) {
|
||||
for (i = 0; i < fx_devs; i++) {
|
||||
uint32_t base;
|
||||
uint32_t basek;
|
||||
base = f1_read_config32(0x40 + (i << 3));
|
||||
|
|
@ -1005,7 +986,7 @@ static void amdk8_domain_set_resources(device_t dev)
|
|||
#endif
|
||||
|
||||
idx = 0x10;
|
||||
for(i = 0; i < FX_DEVS; i++) {
|
||||
for(i = 0; i < fx_devs; i++) {
|
||||
uint32_t base, limit;
|
||||
unsigned basek, limitk, sizek;
|
||||
base = f1_read_config32(0x40 + (i << 3));
|
||||
|
|
@ -1043,7 +1024,7 @@ static void amdk8_domain_set_resources(device_t dev)
|
|||
/* Leave some space for ACPI, PIRQ and MP tables */
|
||||
high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024;
|
||||
high_tables_size = HIGH_TABLES_SIZE * 1024;
|
||||
printk_debug("(split)%xK table at =%08llx\n", HIGH_TABLES_SIZE,
|
||||
printk_debug(" split: %dK table at =%08llx\n", HIGH_TABLES_SIZE,
|
||||
high_tables_base);
|
||||
}
|
||||
#endif
|
||||
|
|
@ -1100,7 +1081,7 @@ static unsigned int amdk8_domain_scan_bus(device_t dev, unsigned int max)
|
|||
* Including enabling relaxed ordering if it is safe.
|
||||
*/
|
||||
get_fx_devs();
|
||||
for(i = 0; i < FX_DEVS; i++) {
|
||||
for(i = 0; i < fx_devs; i++) {
|
||||
device_t f0_dev;
|
||||
f0_dev = __f0_dev[i];
|
||||
if (f0_dev && f0_dev->enabled) {
|
||||
|
|
|
|||
Loading…
Reference in New Issue