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soc/intel/icelake: Add PID based on Icelake EDS 

Change-Id: I2d9e06f06a39dc76a3c1351d7976505d7bd92d10
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/29436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Aamir Bohra 2018-06-30 12:38:43 +05:30 committed by Subrata Banik
parent 5c568e00a5
commit c7267631e2
2 changed files with 14 additions and 32 deletions
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31
src/soc/intel/icelake/bootblock/pch.c
View File

@ -34,9 +34,7 @@
#include <soc/pm.h>
#include <soc/smbus.h>
#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_LP 0x1400
#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_H 0x0980
#define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x0600
#define PCR_PSFX_TO_SHDW_BAR0 0
#define PCR_PSFX_TO_SHDW_BAR1 0x4
#define PCR_PSFX_TO_SHDW_BAR2 0x8
@ -56,20 +54,6 @@
#define PCR_DMI_LPCIOD 0x2770
#define PCR_DMI_LPCIOE 0x2774
static uint32_t get_pmc_reg_base(void)
{
uint8_t pch_series;
pch_series = get_pch_series();
if (pch_series == PCH_H)
return PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_H;
else if (pch_series == PCH_LP)
return PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_LP;
else
return 0;
}
static void soc_config_pwrmbase(void)
{
uint32_t reg32;
@ -113,26 +97,21 @@ void bootblock_pch_early_init(void)
static void soc_config_acpibase(void)
{
uint32_t pmc_reg_value;
uint32_t pmc_base_reg;
pmc_base_reg = get_pmc_reg_base();
if (!pmc_base_reg)
die("Invalid PMC base address\n");
pmc_reg_value = pcr_read32(PID_PSF3, pmc_base_reg +
pmc_reg_value = pcr_read32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE +
PCR_PSFX_TO_SHDW_BAR4);
if (pmc_reg_value != 0xFFFFFFFF) {
/* Disable Io Space before changing the address */
pcr_rmw32(PID_PSF3, pmc_base_reg +
pcr_rmw32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE +
PCR_PSFX_T0_SHDW_PCIEN,
~PCR_PSFX_TO_SHDW_PCIEN_IOEN, 0);
/* Program ABASE in PSF3 PMC space BAR4*/
pcr_write32(PID_PSF3, pmc_base_reg +
pcr_write32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE +
PCR_PSFX_TO_SHDW_BAR4,
ACPI_BASE_ADDRESS);
/* Enable IO Space */
pcr_rmw32(PID_PSF3, pmc_base_reg +
pcr_rmw32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE +
PCR_PSFX_T0_SHDW_PCIEN,
~0, PCR_PSFX_TO_SHDW_PCIEN_IOEN);
}

13
src/soc/intel/icelake/include/soc/pcr_ids.h
View File

@ -20,11 +20,14 @@
*/
#define PID_EMMC 0x52
#define PID_SDX 0x53
#define PID_GPIOCOM4 0x6a
#define PID_GPIOCOM3 0x6b
#define PID_GPIOCOM2 0x6c
#define PID_GPIOCOM1 0x6d
#define PID_GPIOCOM0 0x6e
#define PID_GPIOCOM1 0x6d
#define PID_GPIOCOM2 0x6c
#define PID_GPIOCOM3 0x6b
#define PID_GPIOCOM4 0x6a
#define PID_GPIOCOM5 0x69
#define PID_DMI 0x88
#define PID_PSTH 0x89
#define PID_CSME0 0x90
@ -35,7 +38,7 @@
#define PID_PSF4 0xbd
#define PID_SCS 0xc0
#define PID_RTC 0xc3
#define PID_ITSS 0xc2
#define PID_ITSS 0xc4
#define PID_LPC 0xc7
#define PID_SERIALIO 0xcb