The GPIOs used for UART2 RX and TX were reversed.
Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2726 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -356,19 +356,19 @@ static void uarts_init(struct southbridge_amd_cs5536_config *sb)
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msr.lo |= sb->com2_irq << 28;
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wrmsr(MDD_IRQM_YHIGH, msr);
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/* GPIO3 - UART2_RX */
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/* Set: Output Enable (0x4) */
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outl(GPIOL_3_SET, gpio_addr + GPIOL_OUTPUT_ENABLE);
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/* GPIO4 - UART2_RX */
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/* Set: Output Enable (0x4) */
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outl(GPIOL_4_SET, gpio_addr + GPIOL_OUTPUT_ENABLE);
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/* Set: OUTAUX1 Select (0x10) */
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outl(GPIOL_3_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT);
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outl(GPIOL_4_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT);
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/* GPIO4 - UART2_TX */
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/* Set: Input Enable (0x20) */
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outl(GPIOL_4_SET, gpio_addr + GPIOL_INPUT_ENABLE);
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/* Set: INAUX1 Select (0x34) */
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outl(GPIOL_4_SET, gpio_addr + GPIOL_IN_AUX1_SELECT);
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/* GPIO3 - UART2_TX */
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/* Set: Input Enable (0x20) */
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outl(GPIOL_3_SET, gpio_addr + GPIOL_INPUT_ENABLE);
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/* Set: INAUX1 Select (0x34) */
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outl(GPIOL_3_SET, gpio_addr + GPIOL_IN_AUX1_SELECT);
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/* Set: GPIO 3 + 3 Pull Up (0x18) */
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/* Set: GPIO 3 and 4 Pull Up (0x18) */
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outl(GPIOL_3_SET | GPIOL_4_SET,
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gpio_addr + GPIOL_PULLUP_ENABLE);
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