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soc/rockchip/rk3399/sdram: Add phy_ctrl_reset 

Add support for resetting PHY PCTRL for both channel 0 and 1.

On the ROCKPro64 board this allows getting past a pctl_cfg() failure.

Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: I9f807e318ffc63c568d04518c3edd02c1064e185
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50890
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Moritz Fischer 2021-02-18 14:43:20 -08:00 committed by ron minnich
parent d8f352b4fd
commit c73102d0f5
1 changed files with 13 additions and 0 deletions
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13
src/soc/rockchip/rk3399/sdram.c
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@ -100,6 +100,18 @@ static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
} }
} }
static void phy_pctrl_reset(u32 channel)
{
rkclk_ddr_reset(channel, 1, 1);
udelay(10);
rkclk_ddr_reset(channel, 1, 0);
udelay(10);
rkclk_ddr_reset(channel, 0, 0);
udelay(10);
}
static void phy_dll_bypass_set(u32 channel, static void phy_dll_bypass_set(u32 channel,
struct rk3399_ddr_publ_regs *ddr_publ_regs, u32 freq) struct rk3399_ddr_publ_regs *ddr_publ_regs, u32 freq)
{ {
@ -1083,6 +1095,7 @@ void sdram_init(const struct rk3399_sdram_params *params)
rkclk_configure_ddr(ddr_freq); rkclk_configure_ddr(ddr_freq);
for (channel = 0; channel < 2; channel++) { for (channel = 0; channel < 2; channel++) {
phy_pctrl_reset(channel);
phy_dll_bypass_set(channel, rk3399_ddr_publ[channel], ddr_freq); phy_dll_bypass_set(channel, rk3399_ddr_publ[channel], ddr_freq);
if (channel >= params->num_channels) if (channel >= params->num_channels)