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soc/intel/xeon_sp: Enable build for IO Margining 

This commit enables the build for IO Margining, ensuring that ASPM is
disabled and certain FSP knobs are adjusted in coreboot as below

1. Enable DFXEnable
2. Disable PcieGlobalAspm
3. Disable KtiLinkL1En & KtiLinkL0pEn

Since the FSP UPD does not provide all the necessary knobs for IO
Margining, the following settings need to be applied during the FSP
build process:

1. Enable PcdBiosDfxKnobEnabled
2. Disable PchDmiAspm
3. Enable SataTestMode
4. Enable WmphyMargining
5. Disable IioErrorEn

TEST=Build for IBM sbp1 board.

Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com>
Change-Id: Ie306d12943adb76411d55358548b5cb2eb3a95be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75415
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Naresh Solanki 2023-05-24 10:29:45 +02:00 committed by Lean Sheng Tan
parent 6230d41318
commit c7338085fe
2 changed files with 26 additions and 0 deletions
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9
src/soc/intel/xeon_sp/spr/Kconfig
View File

@ -173,4 +173,13 @@ config INTEL_TXT_HEAP_SIZE
endif # INTEL_TXT
config ENABLE_IO_MARGINING
bool "Enable IO Margining"
default n
depends on !PCIEXP_ASPM
help
Enable support for I/O margining. This is mutually exclusive with
ASPM. This option is intended for debugging and validation and
should normally be disabled.
endif

17
src/soc/intel/xeon_sp/spr/romstage.c
View File

@ -200,6 +200,23 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
config_upd_from_vpd(mupd);
initialize_iio_upd(mupd);
mainboard_memory_init_params(mupd);
if (CONFIG(ENABLE_IO_MARGINING)) {
printk(BIOS_INFO, "IO Margining Enabled.\n");
/* Needed for IO Margining */
mupd->FspmConfig.DFXEnable = 1;
UPD_IIO_PCIE_PORT_CONFIG *iio_pcie_cfg;
int socket;
iio_pcie_cfg = (UPD_IIO_PCIE_PORT_CONFIG *)mupd->FspmConfig.IioPcieConfigTablePtr;
for (socket = 0; socket < MAX_SOCKET; socket++)
iio_pcie_cfg[socket].PcieGlobalAspm = 0;
mupd->FspmConfig.KtiLinkL1En = 0;
mupd->FspmConfig.KtiLinkL0pEn = 0;
}
}
static uint8_t get_error_correction_type(const uint8_t RasModesEnabled)