GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

cpu/amd/microcode: Introduce CBFS access spinlock to avoid IOMMU failure 

When microcode updates are enabled, this fixes an issue identical
to that described in GIT hash 7b22d84d:
 * drivers/pc80: Add optional spinlock for nvram CBFS access

Change-Id: Ib7e8cb171f44833167053ca98a85cca23021dfba
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12063
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Timothy Pearson 2015-08-28 20:48:17 -05:00 committed by Martin Roth
parent 046d217420
commit c764c7488b
3 changed files with 28 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/Kconfig
View File

@ -489,6 +489,10 @@ config HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK
SR565x, that cannot handle concurrent CBFS accesses from SR565x, that cannot handle concurrent CBFS accesses from
multiple APs during early startup. multiple APs during early startup.
config HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK
bool
default n
config HAVE_MONOTONIC_TIMER config HAVE_MONOTONIC_TIMER
def_bool n def_bool n
help help

7
src/arch/x86/include/arch/smp/spinlock.h
View File

@ -1,7 +1,10 @@
#ifndef ARCH_SMP_SPINLOCK_H #ifndef ARCH_SMP_SPINLOCK_H
#define ARCH_SMP_SPINLOCK_H #define ARCH_SMP_SPINLOCK_H
#if !defined(__PRE_RAM__) || IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) || IS_ENABLED(CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK) #if !defined(__PRE_RAM__) \
|| IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) \
|| IS_ENABLED(CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK) \
|| IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
/* /*
* Your basic SMP spinlocks, allowing only a single CPU anywhere * Your basic SMP spinlocks, allowing only a single CPU anywhere
@ -16,6 +19,8 @@ spinlock_t *romstage_console_lock(void);
void initialize_romstage_console_lock(void); void initialize_romstage_console_lock(void);
spinlock_t* romstage_nvram_cbfs_lock(void); spinlock_t* romstage_nvram_cbfs_lock(void);
void initialize_romstage_nvram_cbfs_lock(void); void initialize_romstage_nvram_cbfs_lock(void);
spinlock_t* romstage_microcode_cbfs_lock(void);
void initialize_romstage_microcode_cbfs_lock(void);
#endif #endif
#define SPIN_LOCK_UNLOCKED (spinlock_t) { 1 } #define SPIN_LOCK_UNLOCKED (spinlock_t) { 1 }

19
src/cpu/amd/microcode/microcode.c
View File

@ -20,6 +20,7 @@
#include <cpu/amd/microcode.h> #include <cpu/amd/microcode.h>
#include <cbfs.h> #include <cbfs.h>
#include <arch/io.h> #include <arch/io.h>
#include <smp/spinlock.h>
#define UCODE_DEBUG(fmt, args...) \ #define UCODE_DEBUG(fmt, args...) \
do { printk(BIOS_DEBUG, "[microcode] "fmt, ##args); } while(0) do { printk(BIOS_DEBUG, "[microcode] "fmt, ##args); } while(0)
@ -197,14 +198,30 @@ void amd_update_microcode_from_cbfs(uint32_t equivalent_processor_rev_id)
return; return;
} }
#ifdef __PRE_RAM__
#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
spin_lock(romstage_microcode_cbfs_lock());
#endif
#endif
ucode = cbfs_boot_map_with_leak(microcode_cbfs_file[i], ucode = cbfs_boot_map_with_leak(microcode_cbfs_file[i],
CBFS_TYPE_MICROCODE, &ucode_len); CBFS_TYPE_MICROCODE, &ucode_len);
if (!ucode) { if (!ucode) {
UCODE_DEBUG("microcode file not found. Skipping updates.\n"); UCODE_DEBUG("microcode file not found. Skipping updates.\n");
#ifdef __PRE_RAM__
#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
spin_unlock(romstage_microcode_cbfs_lock());
#endif
#endif
return; return;
} }
amd_update_microcode(ucode, ucode_len, equivalent_processor_rev_id); amd_update_microcode(ucode, ucode_len, equivalent_processor_rev_id);
#ifdef __PRE_RAM__
#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
spin_unlock(romstage_microcode_cbfs_lock());
#endif
#endif
} }
} }