AMD binary PI: add southbridge support for fan control

1. Add functions to support fan control.
2. When IMC firmware is added, the current firmwares' layout
cause build error. There is not enough space to add some firmwares,
so HUDSON_PSP_OFFSET is added to fix this problem.

Change-Id: Ie470a88cb9da256d9f72ea56bf268c15df195784
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/10720
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>

src/southbridge/amd/pi/hudson/Makefile.inc

@@ -45,6 +45,10 @@ ramstage-y += reset.c
 romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
 ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
 romstage-y += early_setup.c
+ifeq ($(CONFIG_HUDSON_IMC_FWM), y)
+romstage-y += imc.c
+ramstage-y += imc.c
+endif
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c smi_util.c
 ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smi_util.c
@@ -109,10 +113,15 @@ HUDSON_PSP_DIRECTORY_POSITION=$(call int-align,\
 	65536)
 HUDSON_PSP_DIRECTORY_SIZE=256
 else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y)
+ifeq ($(CONFIG_HUDSON_IMC_FWM), y)
+HUDSON_PSP_OFFSET=131072
+else
+HUDSON_PSP_OFFSET=0
+endif
 HUDSON_PSP_DIRECTORY_POSITION=$(call int-align,\
 	$(call int-add,\
 		$(HUDSON_FWM_POSITION) $(ROMSIG_SIZE) $(CBFS_HEADER_SIZE) $(XHCI_FWM_SIZE)\
-		$(CBFS_HEADER_SIZE) $(GEC_FWM_SIZE) $(CBFS_HEADER_SIZE) $(IMC_FWM_SIZE) $(CBFS_HEADER_SIZE)),\
+		$(CBFS_HEADER_SIZE) $(GEC_FWM_SIZE) $(CBFS_HEADER_SIZE) $(IMC_FWM_SIZE) $(CBFS_HEADER_SIZE) $(HUDSON_PSP_OFFSET)),\
 	65536)
 HUDSON_PSP_DIRECTORY_SIZE=256
 else

src/southbridge/amd/pi/hudson/acpi/fch.asl

@@ -160,9 +160,11 @@ Method(_INI, 0) {
 	/* Determine the OS we're running on */
 	OSFL()
 
+#if IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE)
 	/* TODO: It is unstable. */
-	//#include "acpi/AmdImc.asl" /* Hudson IMC function */
+	#include "acpi/AmdImc.asl" /* Hudson IMC function */
-	//ITZE() /* enable IMC Fan Control*/
+	ITZE() /* enable IMC Fan Control*/
+#endif
 } /* End Method(_SB._INI) */
 
 Method(OSFL, 0){

src/southbridge/amd/pi/hudson/hudson.c

@@ -30,6 +30,9 @@
 #include "hudson.h"
 #include "smbus.h"
 #include "smi.h"
+#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM)
+#include "fchec.h"
+#endif
 
 /* Offsets from ACPI_MMIO_BASE
  * This is defined by AGESA, but we don't include AGESA headers to avoid
@@ -130,6 +133,12 @@ static void hudson_init(void *chip_info)
 
 static void hudson_final(void *chip_info)
 {
+#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM)
+	agesawrapper_fchecfancontrolservice();
+#if !IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE)
+	enable_imc_thermal_zone();
+#endif
+#endif
 }
 
 struct chip_operations southbridge_amd_pi_hudson_ops = {

src/southbridge/amd/pi/hudson/imc.c

@@ -0,0 +1,105 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#define __SIMPLE_DEVICE__
+
+#include "imc.h"
+#include <arch/io.h>
+#include <device/device.h>
+#include <delay.h>
+#include <Porting.h>
+#include <AGESA.h>
+#include <Lib/amdlib.h>
+#include <Proc/Fch/Common/FchCommonCfg.h>
+#include <Proc/Fch/Fch.h>
+#include <Proc/Fch/FchPlatform.h>
+
+#define VACPI_MMIO_VBASE ((u8 *)ACPI_MMIO_BASE)
+
+void imc_reg_init(void)
+{
+	u8 reg8;
+	/* Init Power Management Block 2 (PM2) Registers.
+	 * Check BKDG for AMD Family 16h for details. */
+	write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x00), 0x06);
+	write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x01), 0x06);
+	write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x02), 0xf7);
+	write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x03), 0xff);
+	write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x04), 0xff);
+
+	write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x10), 0x06);
+	write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x11), 0x06);
+	write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x12), 0xf7);
+	write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x13), 0xff);
+	write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x14), 0xff);
+
+	reg8 = pci_read_config8(PCI_DEV(0, 0x18, 0x3), 0x1E4);
+	reg8 &= 0x8F;
+	reg8 |= 0x10;
+	pci_write_config8(PCI_DEV(0, 0x18, 0x3), 0x1E4, reg8);
+}
+
+#ifndef __PRE_RAM__
+void enable_imc_thermal_zone(void)
+{
+	AMD_CONFIG_PARAMS StdHeader;
+	UINT8 FunNum;
+	UINT8 regs[9];
+	int i;
+
+	regs[0] = 0;
+	regs[1] = 0;
+	FunNum = Fun_80;
+	for (i = 0; i <= 1; i++)
+		WriteECmsg(MSG_REG0 + i, AccessWidth8, &regs[i], &StdHeader);
+	WriteECmsg(MSG_SYS_TO_IMC, AccessWidth8, &FunNum, &StdHeader);
+	WaitForEcLDN9MailboxCmdAck(&StdHeader);
+
+	for (i = 2; i <= 9; i++)
+		ReadECmsg(MSG_REG0 + i, AccessWidth8, &regs[i], &StdHeader);
+
+	/* enable thermal zone 0 */
+	regs[2] |= 1;
+	regs[0] = 0;
+	regs[1] = 0;
+	FunNum = Fun_81;
+	for (i = 0; i <= 9; i++)
+		WriteECmsg(MSG_REG0 + i, AccessWidth8, &regs[i], &StdHeader);
+	WriteECmsg(MSG_SYS_TO_IMC, AccessWidth8, &FunNum, &StdHeader);
+	WaitForEcLDN9MailboxCmdAck(&StdHeader);
+}
+#endif
+
+/* Bettong Hardware Monitor Fan Control
+ * Hardware limitation:
+ *  HWM will fail to read the input temperature via I2C if other
+ *  software switches the I2C address.  AMD recommends using IMC
+ *  to control fans, instead of HWM.
+ */
+void oem_fan_control(FCH_DATA_BLOCK *FchParams)
+{
+	/* Enable IMC fan control. the recommand way */
+	imc_reg_init();
+
+	FchParams->Imc.ImcEnable = TRUE;
+	FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */
+	FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
+
+	LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader);
+}

src/southbridge/amd/pi/hudson/imc.h

@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef HUDSON_IMC_H
+#define HUDSON_IMC_H
+
+#include "Porting.h"
+#include "AGESA.h"
+#include <FchCommonCfg.h>
+
+void imc_reg_init(void);
+void enable_imc_thermal_zone(void);
+void oem_fan_control(FCH_DATA_BLOCK *FchParams);
+
+#endif