google/oak: Support cr50 over I2C on rowan

This patch enables TPM2 using cr50 over I2C for the Rowan board, and
adds an mt8173 specific TPM IRQ polling function. The function relies on
the appropriate EINT input configured to trigger the ready status on
the rising edge.

The cr50 TPM is on I2C address 0x50.

The cr50 interrupt GPIO is also made available for use by depthcharge
via the coreboot tables.

BRANCH=none
BUG=b:36786804
TEST=Boot rowan w/ serial enabled, verify coreboot and depthcharge are
 configured to use IRQ flow control when talking to the Cr50 TPM.

Change-Id: If6cdd0e39e4ac86538f27f322c55c329179ee084
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/19364
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>

src/mainboard/google/oak/Kconfig

@@ -18,6 +18,12 @@ config BOARD_GOOGLE_OAK_COMMON
 
 if BOARD_GOOGLE_OAK_COMMON
 
+config OAK_HAS_TPM2
+	bool
+	default y if BOARD_GOOGLE_ROWAN
+	default n
+	select MAINBOARD_HAS_I2C_TPM_CR50
+
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select SOC_MEDIATEK_MT8173
@@ -56,7 +62,8 @@ config DRIVER_TPM_I2C_BUS
 
 config DRIVER_TPM_I2C_ADDR
 	hex
-	default 0x20
+	default 0x20 if !OAK_HAS_TPM2
+	default 0x50 if OAK_HAS_TPM2
 
 config BOOT_DEVICE_SPI_FLASH_BUS
 	int

src/mainboard/google/oak/Makefile.inc

@@ -17,16 +17,20 @@ bootblock-y += bootblock.c
 bootblock-y += memlayout.ld
 bootblock-y += chromeos.c
 bootblock-y += boardid.c
+bootblock-$(CONFIG_OAK_HAS_TPM2) += tpm_tis.c
 
 verstage-y += chromeos.c
 verstage-y += memlayout.ld
+verstage-$(CONFIG_OAK_HAS_TPM2) += tpm_tis.c
 
 romstage-y += chromeos.c
 romstage-y += romstage.c sdram_configs.c
 romstage-y += memlayout.ld
 romstage-y += boardid.c
+romstage-$(CONFIG_OAK_HAS_TPM2) += tpm_tis.c
 
 ramstage-y += mainboard.c
 ramstage-y += chromeos.c
 ramstage-y += memlayout.ld
 ramstage-y += boardid.c
+ramstage-$(CONFIG_OAK_HAS_TPM2) += tpm_tis.c

src/mainboard/google/oak/bootblock.c

@@ -88,6 +88,9 @@ void bootblock_mainboard_init(void)
 	/* Init i2c bus 2 Timing register for TPM */
 	mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS);
 
+	if (IS_ENABLED(CONFIG_OAK_HAS_TPM2))
+		gpio_eint_configure(CR50_IRQ, IRQ_TYPE_EDGE_RISING);
+
 	mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD1_MASK, 6*MHz);
 
 	setup_chromeos_gpios();

src/mainboard/google/oak/chromeos.c

@@ -42,6 +42,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 		{POWER_BUTTON, ACTIVE_HIGH, -1, "power"},
 		{EC_IN_RW, ACTIVE_HIGH, -1, "EC in RW"},
 		{EC_IRQ, ACTIVE_LOW, -1, "EC interrupt"},
+		{CR50_IRQ, ACTIVE_HIGH, -1, "TPM interrupt"},
 	};
 	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
 }

src/mainboard/google/oak/gpio.h

@@ -42,6 +42,8 @@ enum {
 	EC_IN_RW	= PAD_DAIPCMIN,
 	/* EC AP suspend */
 	EC_SUSPEND_L	= PAD_KPROW1,
+	/* Cr50 interrupt */
+	CR50_IRQ	= PAD_EINT16,
 };
 
 void setup_chromeos_gpios(void);

src/mainboard/google/oak/tpm_tis.c

@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <gpio.h>
+#include <tpm.h>
+
+#include "gpio.h"
+
+int tis_plat_irq_status(void)
+{
+	return gpio_eint_poll(CR50_IRQ);
+}

src/soc/mediatek/mt8173/Makefile.inc

@@ -40,6 +40,7 @@ verstage-$(CONFIG_DRIVERS_UART) += uart.c
 verstage-y += timer.c
 verstage-y += wdt.c
 verstage-$(CONFIG_SPI_FLASH) += flash_controller.c
+verstage-y += gpio.c
 
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