diff --git a/Documentation/Intel/SoC/quark.html b/Documentation/Intel/SoC/quark.html index bd32b242ec..ea704a94c5 100644 --- a/Documentation/Intel/SoC/quark.html +++ b/Documentation/Intel/SoC/quark.html @@ -53,21 +53,58 @@ Build Instructions:
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x03F8
+
+with:
+#
+# Quark configuration
+#
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|1
+
+#
+# Specify Galileo HSUART1 serial port
+#
+[PcdsPatchableInModule.common]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialPciDeviceInfo|{0xff}
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0xA0019000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride|4
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate|44236800
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|921600
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialLineControl|3 # 8-bits, no parity
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialDetectCable|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|1 # Enable FIFO
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialExtendedTxFifoSize|16
+
+ *_GCC48_IA32_CC_FLAGS = DEF(GCC48_IA32_CC_FLAGS) -Os -march=i586
+ build -p CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc -a IA32 -t GCC48 -b DEBUG -DDEBUG_PROPERTY_MASK=0x27 -DDEBUG_PRINT_ERROR_LEVEL=0x80000042
-ls Build/CorebootPayloadPkg/DEBUG_GCC48/FV/UEFIPAYLOAD.fd
+ls Build/CorebootPayloadPkgIA32/DEBUG_GCC48/FV/UEFIPAYLOAD.fd
+ build -p CorebootPayloadPkg\CorebootPayloadPkgIa32.dsc -a IA32 -t VS2012x86 -b DEBUG -DDEBUG_PROPERTY_MASK=0x27 -DDEBUG_PRINT_ERROR_LEVEL=0x80000042
-dir Build\CorebootPayloadPkg\DEBUG_VS2012x86\FV\UEFIPAYLOAD.fd
+dir Build\CorebootPayloadPkgIA32\DEBUG_VS2012x86\FV\UEFIPAYLOAD.fd
Modified: 10 February 2016
+Modified: 20 February 2016