mb/google/hades: Add baseboard device tree
Add minimum device tree. Leave IOs default disable to optimize variant override complexity. BUG=b:271199379 TEST=abuild -a -x -c max -p none -t google/brya -b hades Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ibb056c07193b4265352a9ec74829dcf02a9340bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/73415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
This commit is contained in:
Eric Lai
Martin L Roth
parent
325db346c2
commit
c7b16bebbc
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@ -1,4 +1,124 @@
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chip soc/intel/alderlake
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chip soc/intel/alderlake
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# GPE configuration
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register "pmc_gpe0_dw0" = "GPP_A"
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register "pmc_gpe0_dw1" = "GPP_E"
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register "pmc_gpe0_dw2" = "GPP_F"
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# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
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register "gen1_dec" = "0x00fc0801"
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register "gen2_dec" = "0x000c0201"
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# EC memory map range is 0x900-0x9ff
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register "gen3_dec" = "0x00fc0901"
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# S0ix enable
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register "s0ix_enable" = "1"
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# DPTF enable
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register "dptf_enable" = "1"
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register "tcc_offset" = "10" # TCC of 90
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# Enable CNVi BT
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register "cnvi_bt_core" = "true"
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register "usb2_ports[0]" = "USB2_PORT_EMPTY"
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register "usb2_ports[1]" = "USB2_PORT_EMPTY"
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register "usb2_ports[2]" = "USB2_PORT_EMPTY"
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register "usb2_ports[3]" = "USB2_PORT_EMPTY"
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register "usb2_ports[4]" = "USB2_PORT_EMPTY"
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register "usb2_ports[5]" = "USB2_PORT_EMPTY"
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register "usb2_ports[6]" = "USB2_PORT_EMPTY"
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register "usb2_ports[7]" = "USB2_PORT_EMPTY"
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register "usb2_ports[8]" = "USB2_PORT_EMPTY"
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register "usb2_ports[9]" = "USB2_PORT_EMPTY"
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register "usb3_ports[0]" = "USB3_PORT_EMPTY"
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register "usb3_ports[1]" = "USB3_PORT_EMPTY"
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register "usb3_ports[2]" = "USB3_PORT_EMPTY"
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register "usb3_ports[3]" = "USB3_PORT_EMPTY"
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register "tcss_ports[0]" = "TCSS_PORT_EMPTY"
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register "tcss_ports[1]" = "TCSS_PORT_EMPTY"
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register "tcss_ports[2]" = "TCSS_PORT_EMPTY"
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register "tcss_ports[3]" = "TCSS_PORT_EMPTY"
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register "pch_slp_s3_min_assertion_width" = "SLP_S3_ASSERTION_50_MS"
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register "pch_slp_s4_min_assertion_width" = "SLP_S4_ASSERTION_1S"
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register "pch_slp_sus_min_assertion_width" = "SLP_SUS_ASSERTION_1_S"
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register "pch_slp_a_min_assertion_width" = "SLP_A_ASSERTION_98_MS"
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register "pch_reset_power_cycle_duration" = "POWER_CYCLE_DURATION_1S"
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# HD Audio
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register "pch_hda_dsp_enable" = "1"
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register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
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register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
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register "pch_hda_idisp_codec_enable" = "1"
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# FIVR RFI Spread Spectrum 1.5%
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register "fivr_spread_spectrum" = "FIVR_SS_1_5"
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# Disable C state auto-demotion for all brya baseboards
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register "disable_c1_state_auto_demotion" = "1"
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register "serial_io_uart_mode" = "{
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[PchSerialIoIndexUART0] = PchSerialIoPci,
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[PchSerialIoIndexUART1] = PchSerialIoDisabled,
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[PchSerialIoIndexUART2] = PchSerialIoDisabled,
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}"
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device domain 0 on
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device domain 0 on
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# The timing values can be derived from datasheet of display panel
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# You can use EDID string to identify the type of display on the board
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# use below command to get display info from EDID
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# strings /sys/devices/pci0000:00/0000:00:02.0/drm/card0/card0-eDP-1/edid
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# refer to display PRM document (Volume 2b: Command Reference: Registers)
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# for more info on display control registers
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# https://01.org/linuxgraphics/documentation/hardware-specification-prms
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#+-----------------------------+---------------------------------------+-----+
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#| Intel docs | devicetree.cb | eDP |
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#+-----------------------------+---------------------------------------+-----+
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#| Power up delay | `gpu_panel_power_up_delay` | T3 |
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#+-----------------------------+---------------------------------------+-----+
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#| Power on to backlight on | `gpu_panel_power_backlight_on_delay` | T7 |
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#+-----------------------------+---------------------------------------+-----+
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#| Power Down delay | `gpu_panel_power_down_delay` | T10 |
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#+-----------------------------+---------------------------------------+-----+
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#| Backlight off to power down | `gpu_panel_power_backlight_off_delay` | T9 |
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#+-----------------------------+---------------------------------------+-----+
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#| Power Cycle Delay | `gpu_panel_power_cycle_delay` | T12 |
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#+-----------------------------+---------------------------------------+-----+
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device ref igpu on
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register "panel_cfg" = "{
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.up_delay_ms = 200,
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.down_delay_ms = 50,
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.cycle_delay_ms = 500,
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.backlight_on_delay_ms = 1,
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.backlight_off_delay_ms = 200,
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.backlight_pwm_hz = 200,
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}"
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end
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device ref dtt on end
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device ref tcss_xhci on end
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device ref xhci on end
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device ref shared_sram on end
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device ref cnvi_wifi on
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chip drivers/wifi/generic
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register "wake" = "GPE0_PME_B0"
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register "add_acpi_dma_property" = "true"
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device generic 0 on end
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end
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end
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device ref heci1 on end
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device ref sata on end
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device ref uart0 on end
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device ref gspi1 on end
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device ref pch_espi on
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chip ec/google/chromeec
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device pnp 0c09.0 on end
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end
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end
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device ref hda on end
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end
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end
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end
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end
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