From c7b23e9dc8d2efca8476c46b4879e4958b420f36 Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Tue, 7 Aug 2018 12:16:09 +0530 Subject: [PATCH] src/soc/intel/common: Configure the gspi chip select state correctly This implementation updates the chip select control register programming in gspi controller setup call to program the correct bit fields for chip select state. Change-Id: Ifab37b0003f09a680024d5b155ab0bb157920a53 Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/27889 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Furquan Shaikh --- src/soc/intel/common/block/gspi/gspi.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c index 35c34cecbc..fc7dd46ad8 100644 --- a/src/soc/intel/common/block/gspi/gspi.c +++ b/src/soc/intel/common/block/gspi/gspi.c @@ -481,12 +481,9 @@ static int gspi_ctrlr_setup(const struct spi_slave *dev) cs_ctrl = CS_MODE_SW | CS_0; pol = gspi_csctrl_polarity(cfg.cs_polarity); cs_ctrl |= pol << CS_0_POL_SHIFT; - cs_ctrl |= gspi_csctrl_state(pol, CS_DEASSERT); + cs_ctrl |= gspi_csctrl_state(pol, CS_DEASSERT) << CS_STATE_SHIFT; gspi_write_mmio_reg(p, SPI_CS_CONTROL, cs_ctrl); - /* De-assert chip select. */ - __gspi_cs_change(p, CS_DEASSERT); - /* Disable SPI controller. */ gspi_write_mmio_reg(p, SSCR0, SSCR0_SSE_DISABLE);