From c7ca0f2e33f06c3683cc1db41f83e3e5f31d566d Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 8 Sep 2021 14:22:12 +0200 Subject: [PATCH] soc/intel/broadwell/pcie.c: Simplify AND-mask There's no need to mask out bit 11, as it is unconditionally set. For some reason, this changes the resulting coreboot image. Also simplify another PCI operation with a redundant AND-mask. Change-Id: I5492acd5f9c61db83a07ce7c1f6b887768c3eadf Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/57499 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Felix Held --- src/soc/intel/broadwell/pch/pcie.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/broadwell/pch/pcie.c b/src/soc/intel/broadwell/pch/pcie.c index 28d858f2b0..29915d6e13 100644 --- a/src/soc/intel/broadwell/pch/pcie.c +++ b/src/soc/intel/broadwell/pch/pcie.c @@ -516,8 +516,8 @@ static void pch_pcie_early(struct device *dev) } /* Enable LTR in Root Port. Disable OBFF. */ - pci_update_config32(dev, 0x64, ~(1 << 11) & ~(3 << 18), (1 << 11)); - pci_update_config32(dev, 0x68, ~(1 << 10), (1 << 10)); + pci_update_config32(dev, 0x64, ~(3 << 18), (1 << 11)); + pci_or_config32(dev, 0x68, 1 << 10); pci_update_config32(dev, 0x318, ~(0xffff << 16), (0x1414 << 16));