siemens/mc_apl1: Program eMMC DLL settings
Program eMMC DLL settings for mc_apl1 mainboard, after that system can boot up with eMMC successfully. Change-Id: I3d60f66ec5c7e09540ccda59f244aac6f78bf954 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/19712 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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@ -12,6 +12,35 @@ chip soc/intel/apollolake
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register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
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register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
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# EMMC TX DATA Delay 1
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# Refer to EDS-Vol2-22.3.
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# [14:8] steps of delay for HS400, each 125ps.
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# [6:0] steps of delay for SDR104/HS200, each 125ps.
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register "emmc_tx_data_cntl1" = "0x0C16"
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# EMMC TX DATA Delay 2
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# Refer to EDS-Vol2-22.3.
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# [30:24] steps of delay for SDR50, each 125ps.
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# [22:16] steps of delay for DDR50, each 125ps.
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# [14:8] steps of delay for SDR25/HS50, each 125ps.
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# [6:0] steps of delay for SDR12, each 125ps.
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register "emmc_tx_data_cntl2" = "0x28162828"
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# EMMC RX CMD/DATA Delay 1
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# Refer to EDS-Vol2-22.3.
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# [30:24] steps of delay for SDR50, each 125ps.
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# [22:16] steps of delay for DDR50, each 125ps.
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# [14:8] steps of delay for SDR25/HS50, each 125ps.
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# [6:0] steps of delay for SDR12, each 125ps.
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register "emmc_rx_cmd_data_cntl1" = "0x00181717"
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# EMMC RX CMD/DATA Delay 2
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# Refer to EDS-Vol2-22.3.
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# [17:16] stands for Rx Clock before Output Buffer
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# [14:8] steps of delay for Auto Tuning Mode, each 125ps.
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# [6:0] steps of delay for HS200, each 125ps.
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register "emmc_rx_cmd_data_cntl2" = "0x10008"
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device domain 0 on
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device pci 00.0 on end # - Host Bridge
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device pci 00.1 off end # - DPTF
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