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soc/intel: Refactor `xdci_can_enable()` function 

The same pattern appears on all `xdci_can_enable()` call sites. Move the
logic inside the function and take the xDCI devfn as parameter.

Change-Id: I94c24c10c7fc7c5b4938cffca17bdfb853c7bd59
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Angel Pons 2021-06-23 12:39:22 +02:00 committed by Patrick Georgi
parent 3657187789
commit c7cfe0ba54
10 changed files with 16 additions and 35 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/soc/intel/alderlake/fsp_params.c
View File

@ -371,10 +371,7 @@ static void fill_fsps_xhci_params(FSP_S_CONFIG *s_cfg,
static void fill_fsps_xdci_params(FSP_S_CONFIG *s_cfg,
const struct soc_intel_alderlake_config *config)
{
/* Enable xDCI controller if enabled in devicetree and allowed */
if (!xdci_can_enable())
devfn_disable(pci_root_bus(), PCH_DEVFN_USBOTG);
s_cfg->XdciEnable = is_devfn_enabled(PCH_DEVFN_USBOTG);
s_cfg->XdciEnable = xdci_can_enable(PCH_DEVFN_USBOTG);
}
static void fill_fsps_uart_params(FSP_S_CONFIG *s_cfg,

5
src/soc/intel/apollolake/chip.c
View File

@ -680,10 +680,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
else
apl_fsp_silicon_init_params_cb(cfg, silconfig);
/* Enable xDCI controller if enabled in devicetree and allowed */
if (!xdci_can_enable())
devfn_disable(pci_root_bus(), PCH_DEVFN_XDCI);
silconfig->UsbOtg = is_devfn_enabled(PCH_DEVFN_XDCI);
silconfig->UsbOtg = xdci_can_enable(PCH_DEVFN_XDCI);
silconfig->VmxEnable = CONFIG(ENABLE_VMX);

5
src/soc/intel/cannonlake/fsp_params.c
View File

@ -497,10 +497,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
}
}
/* Enable xDCI controller if enabled in devicetree and allowed */
if (!xdci_can_enable())
devfn_disable(pci_root_bus(), PCH_DEVFN_USBOTG);
params->XdciEnable = is_devfn_enabled(PCH_DEVFN_USBOTG);
params->XdciEnable = xdci_can_enable(PCH_DEVFN_USBOTG);
/* Set Debug serial port */
params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;

2
src/soc/intel/common/block/include/intelblocks/xdci.h
View File

@ -4,6 +4,6 @@
#define SOC_INTEL_COMMON_BLOCK_XDCI_H
void soc_xdci_init(struct device *dev);
int xdci_can_enable(void);
bool xdci_can_enable(unsigned int xdci_devfn);
#endif /* SOC_INTEL_COMMON_BLOCK_XDCI_H */

9
src/soc/intel/common/block/xdci/xdci.c
View File

@ -8,9 +8,14 @@
__weak void soc_xdci_init(struct device *dev) { /* no-op */ }
int xdci_can_enable(void)
bool xdci_can_enable(unsigned int xdci_devfn)
{
return vboot_can_enable_udc();
/* Enable xDCI controller if enabled in devicetree and allowed */
if (!vboot_can_enable_udc()) {
devfn_disable(pci_root_bus(), xdci_devfn);
return false;
}
return is_devfn_enabled(xdci_devfn);
}
static struct device_operations usb_xdci_ops = {

5
src/soc/intel/elkhartlake/fsp_params.c
View File

@ -181,10 +181,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->UsbClockGatingEnable = 1;
params->UsbPowerGatingEnable = 1;
/* Enable xDCI controller if enabled in devicetree and allowed */
if (!xdci_can_enable())
devfn_disable(pci_root_bus(), PCH_DEVFN_USBOTG);
params->XdciEnable = is_devfn_enabled(PCH_DEVFN_USBOTG);
params->XdciEnable = xdci_can_enable(PCH_DEVFN_USBOTG);
/* PCIe root ports config */
for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) {

5
src/soc/intel/icelake/fsp_params.c
View File

@ -137,10 +137,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
}
}
/* Enable xDCI controller if enabled in devicetree and allowed */
if (!xdci_can_enable())
devfn_disable(pci_root_bus(), PCH_DEVFN_USBOTG);
params->XdciEnable = is_devfn_enabled(PCH_DEVFN_USBOTG);
params->XdciEnable = xdci_can_enable(PCH_DEVFN_USBOTG);
/* PCI Express */
for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) {

5
src/soc/intel/jasperlake/fsp_params.c
View File

@ -157,10 +157,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
if (params->ScsEmmcEnabled)
params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
/* Enable xDCI controller if enabled in devicetree and allowed */
if (!xdci_can_enable())
devfn_disable(pci_root_bus(), PCH_DEVFN_USBOTG);
params->XdciEnable = is_devfn_enabled(PCH_DEVFN_USBOTG);
params->XdciEnable = xdci_can_enable(PCH_DEVFN_USBOTG);
/* Provide correct UART number for FSP debug logs */
params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;

5
src/soc/intel/skylake/chip.c
View File

@ -456,10 +456,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
/* Show SPI controller if enabled in devicetree.cb */
params->ShowSpiController = is_devfn_enabled(PCH_DEVFN_SPI);
/* Enable xDCI controller if enabled in devicetree and allowed */
if (!xdci_can_enable())
devfn_disable(pci_root_bus(), PCH_DEVFN_USBOTG);
params->XdciEnable = is_devfn_enabled(PCH_DEVFN_USBOTG);
params->XdciEnable = xdci_can_enable(PCH_DEVFN_USBOTG);
/* Enable or disable Gaussian Mixture Model in devicetree */
params->GmmEnable = is_devfn_enabled(SA_DEVFN_GMM);

5
src/soc/intel/tigerlake/fsp_params.c
View File

@ -462,10 +462,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
config->tcss_ports[i].ocpin;
}
/* Enable xDCI controller if enabled in devicetree and allowed */
if (!xdci_can_enable())
devfn_disable(pci_root_bus(), PCH_DEVFN_USBOTG);
params->XdciEnable = is_devfn_enabled(PCH_DEVFN_USBOTG);
params->XdciEnable = xdci_can_enable(PCH_DEVFN_USBOTG);
/* PCH UART selection for FSP Debug */
params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;