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Attached patch removes unnecessary IRQ routing info (for ACPI, mptable etc needs to be fixed too). The devicetree.cb changes should reflect now the real board configuration. It has one 16x slot and 1x slot (GPP device 9) and GPP device a is onboard ethernet. The mainboard.c now presents the board name and 

I removed the gpio asserts - I think those are not used here.

The pcie 1x slot works, the x1 card I have does not work in 16x slot, but in orig bios I cannot see it any slot, so it is kind of better.

The classic PCI slot works fine too. However it seems SATA has some issues.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz> 
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5720 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Rudolf Marek 2010-08-17 21:03:17 +00:00
parent da71ba5284
commit c7d2773e12
4 changed files with 48 additions and 226 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

171
src/mainboard/asrock/939a785gmh/acpi/routing.asl
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@ -32,31 +32,12 @@ Scope(\_SB) {
/* Bus 0, Dev 0 - RS780 Host Controller */ /* Bus 0, Dev 0 - RS780 Host Controller */
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
Package(){0x0002FFFF, 0, INTC, 0 }, Package(){0x0002FFFF, 0, INTC, 0 },
Package(){0x0002FFFF, 1, INTD, 0 }, Package(){0x0002FFFF, 1, INTD, 0 },
Package(){0x0002FFFF, 2, INTA, 0 }, Package(){0x0002FFFF, 2, INTA, 0 },
Package(){0x0002FFFF, 3, INTB, 0 }, Package(){0x0002FFFF, 3, INTB, 0 },
/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
Package(){0x0004FFFF, 0, INTA, 0 },
Package(){0x0004FFFF, 1, INTB, 0 },
Package(){0x0004FFFF, 2, INTC, 0 },
Package(){0x0004FFFF, 3, INTD, 0 },
/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
/* Package(){0x0005FFFF, 0, INTB, 0 }, */
/* Package(){0x0005FFFF, 1, INTC, 0 }, */
/* Package(){0x0005FFFF, 2, INTD, 0 }, */
/* Package(){0x0005FFFF, 3, INTA, 0 }, */
/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
Package(){0x0006FFFF, 0, INTC, 0 },
Package(){0x0006FFFF, 1, INTD, 0 },
Package(){0x0006FFFF, 2, INTA, 0 },
Package(){0x0006FFFF, 3, INTB, 0 },
/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
Package(){0x0007FFFF, 0, INTD, 0 },
Package(){0x0007FFFF, 1, INTA, 0 },
Package(){0x0007FFFF, 2, INTB, 0 },
Package(){0x0007FFFF, 3, INTC, 0 },
/* Bus 0, Funct 8 - Southbridge port (normally hidden) */ /* Bus 0, Funct 8 - Southbridge port (normally hidden) */
/* SB devices */ /* SB devices */
@ -69,12 +50,12 @@ Scope(\_SB) {
Package(){0x0012FFFF, 0, INTA, 0 }, Package(){0x0012FFFF, 0, INTA, 0 },
Package(){0x0012FFFF, 1, INTB, 0 }, Package(){0x0012FFFF, 1, INTB, 0 },
Package(){0x0012FFFF, 2, INTC, 0 }, Package(){0x0012FFFF, 2, INTC, 0 },
Package(){0x0012FFFF, 3, INTD, 0 },
Package(){0x0013FFFF, 0, INTC, 0 }, Package(){0x0013FFFF, 0, INTC, 0 },
Package(){0x0013FFFF, 1, INTD, 0 }, Package(){0x0013FFFF, 1, INTD, 0 },
Package(){0x0013FFFF, 2, INTA, 0 }, Package(){0x0013FFFF, 2, INTA, 0 },
Package(){0x0013FFFF, 3, INTB, 0 },
/* Package(){0x0014FFFF, 1, INTA, 0 }, */
/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
Package(){0x0014FFFF, 0, INTA, 0 }, Package(){0x0014FFFF, 0, INTA, 0 },
@ -93,47 +74,21 @@ Scope(\_SB) {
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
Package(){0x0002FFFF, 0, 0, 18 }, Package(){0x0002FFFF, 0, 0, 18 },
/* Package(){0x0002FFFF, 1, 0, 19 }, */ Package(){0x0002FFFF, 1, 0, 19 },
/* Package(){0x0002FFFF, 2, 0, 16 }, */ Package(){0x0002FFFF, 2, 0, 16 },
/* Package(){0x0002FFFF, 3, 0, 17 }, */ Package(){0x0002FFFF, 3, 0, 17 },
/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ /* Bus 0, Dev 9 - PCIe x1 slot */
Package(){0x0003FFFF, 0, 0, 19 },
/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
Package(){0x0004FFFF, 0, 0, 16 },
/* Package(){0x0004FFFF, 1, 0, 17 }, */
/* Package(){0x0004FFFF, 2, 0, 18 }, */
/* Package(){0x0004FFFF, 3, 0, 19 }, */
/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
/* Package(){0x0005FFFF, 0, 0, 17 }, */
/* Package(){0x0005FFFF, 1, 0, 18 }, */
/* Package(){0x0005FFFF, 2, 0, 19 }, */
/* Package(){0x0005FFFF, 3, 0, 16 }, */
/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
/* Package(){0x0006FFFF, 0, 0, 18 }, */
/* Package(){0x0006FFFF, 1, 0, 19 }, */
/* Package(){0x0006FFFF, 2, 0, 16 }, */
/* Package(){0x0006FFFF, 3, 0, 17 }, */
/* Bus 0, Dev 7 - PCIe Bridge for network card */
/* Package(){0x0007FFFF, 0, 0, 19 }, */
/* Package(){0x0007FFFF, 1, 0, 16 }, */
/* Package(){0x0007FFFF, 2, 0, 17 }, */
/* Package(){0x0007FFFF, 3, 0, 18 }, */
/* Bus 0, Dev 9 - PCIe Bridge for network card */
Package(){0x0009FFFF, 0, 0, 17 }, Package(){0x0009FFFF, 0, 0, 17 },
/* Package(){0x0009FFFF, 1, 0, 16 }, */ Package(){0x0009FFFF, 1, 0, 18 },
/* Package(){0x0009FFFF, 2, 0, 17 }, */ Package(){0x0009FFFF, 2, 0, 19 },
/* Package(){0x0009FFFF, 3, 0, 18 }, */ Package(){0x0009FFFF, 3, 0, 10 },
/* Bus 0, Dev A - PCIe Bridge for network card */
/* Bus 0, Dev A - PCIe internal ethernet */
Package(){0x000AFFFF, 0, 0, 18 }, Package(){0x000AFFFF, 0, 0, 18 },
/* Package(){0x000AFFFF, 1, 0, 16 }, */ Package(){0x000AFFFF, 1, 0, 19 },
/* Package(){0x000AFFFF, 2, 0, 17 }, */ Package(){0x000AFFFF, 2, 0, 16 },
/* Package(){0x000AFFFF, 3, 0, 18 }, */ Package(){0x000AFFFF, 3, 0, 17 },
/* Bus 0, Funct 8 - Southbridge port (normally hidden) */ /* Bus 0, Funct 8 - Southbridge port (normally hidden) */
/* SB devices in APIC mode */ /* SB devices in APIC mode */
@ -146,41 +101,34 @@ Scope(\_SB) {
Package(){0x0012FFFF, 0, 0, 16 }, Package(){0x0012FFFF, 0, 0, 16 },
Package(){0x0012FFFF, 1, 0, 17 }, Package(){0x0012FFFF, 1, 0, 17 },
Package(){0x0012FFFF, 2, 0, 18 }, Package(){0x0012FFFF, 2, 0, 18 },
Package(){0x0012FFFF, 3, 0, 19 },
Package(){0x0013FFFF, 0, 0, 18 }, Package(){0x0013FFFF, 0, 0, 18 },
Package(){0x0013FFFF, 1, 0, 19 }, Package(){0x0013FFFF, 1, 0, 19 },
Package(){0x0013FFFF, 2, 0, 16 }, Package(){0x0013FFFF, 2, 0, 16 },
Package(){0x0013FFFF, 3, 0, 17 },
/* Package(){0x00140000, 0, 0, 16 }, */
/* Package(){0x00130004, 2, 0, 18 }, */
/* Package(){0x00130005, 3, 0, 19 }, */
/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
Package(){0x0014FFFF, 0, 0, 16 }, Package(){0x0014FFFF, 0, 0, 16 },
Package(){0x0014FFFF, 1, 0, 17 }, Package(){0x0014FFFF, 1, 0, 17 },
Package(){0x0014FFFF, 2, 0, 18 }, Package(){0x0014FFFF, 2, 0, 18 },
Package(){0x0014FFFF, 3, 0, 19 }, Package(){0x0014FFFF, 3, 0, 19 },
/* Package(){0x00140004, 2, 0, 18 }, */
/* Package(){0x00140004, 3, 0, 19 }, */
/* Package(){0x00140005, 1, 0, 17 }, */
/* Package(){0x00140006, 1, 0, 17 }, */
}) })
Name(PR1, Package(){ Name(PR1, Package(){
/* Internal graphics - RS780 VGA, Bus1, Dev5 */ /* Internal graphics - RS780 VGA, Bus1, Dev5 */
Package(){0x0005FFFF, 0, INTA, 0 }, Package(){0x0005FFFF, 0, INTC, 0 },
Package(){0x0005FFFF, 1, INTB, 0 }, Package(){0x0005FFFF, 1, INTD, 0 },
Package(){0x0005FFFF, 2, INTC, 0 }, Package(){0x0005FFFF, 2, INTA, 0 },
Package(){0x0005FFFF, 3, INTD, 0 }, Package(){0x0005FFFF, 3, INTB, 0 },
}) })
Name(APR1, Package(){ Name(APR1, Package(){
/* Internal graphics - RS780 VGA, Bus1, Dev5 */ /* Internal graphics - RS780 VGA, Bus1, Dev5 */
Package(){0x0005FFFF, 0, 0, 18 }, Package(){0x0005FFFF, 0, 0, 18 },
Package(){0x0005FFFF, 1, 0, 19 }, Package(){0x0005FFFF, 1, 0, 19 },
/* Package(){0x0005FFFF, 2, 0, 20 }, */ Package(){0x0005FFFF, 2, 0, 16 },
/* Package(){0x0005FFFF, 3, 0, 17 }, */ Package(){0x0005FFFF, 3, 0, 11 },
}) })
Name(PS2, Package(){ Name(PS2, Package(){
@ -198,72 +146,9 @@ Scope(\_SB) {
Package(){0x0000FFFF, 2, 0, 16 }, Package(){0x0000FFFF, 2, 0, 16 },
Package(){0x0000FFFF, 3, 0, 17 }, Package(){0x0000FFFF, 3, 0, 17 },
}) })
Name(PS4, Package(){
/* PCIe slot - Hooked to PCIe slot 4 */
Package(){0x0000FFFF, 0, INTA, 0 },
Package(){0x0000FFFF, 1, INTB, 0 },
Package(){0x0000FFFF, 2, INTC, 0 },
Package(){0x0000FFFF, 3, INTD, 0 },
})
Name(APS4, Package(){
/* PCIe slot - Hooked to PCIe slot 4 */
Package(){0x0000FFFF, 0, 0, 16 },
Package(){0x0000FFFF, 1, 0, 17 },
Package(){0x0000FFFF, 2, 0, 18 },
Package(){0x0000FFFF, 3, 0, 19 },
})
Name(PS5, Package(){
/* PCIe slot - Hooked to PCIe slot 5 */
Package(){0x0000FFFF, 0, INTB, 0 },
Package(){0x0000FFFF, 1, INTC, 0 },
Package(){0x0000FFFF, 2, INTD, 0 },
Package(){0x0000FFFF, 3, INTA, 0 },
})
Name(APS5, Package(){
/* PCIe slot - Hooked to PCIe slot 5 */
Package(){0x0000FFFF, 0, 0, 17 },
Package(){0x0000FFFF, 1, 0, 18 },
Package(){0x0000FFFF, 2, 0, 19 },
Package(){0x0000FFFF, 3, 0, 16 },
})
Name(PS6, Package(){
/* PCIe slot - Hooked to PCIe slot 6 */
Package(){0x0000FFFF, 0, INTC, 0 },
Package(){0x0000FFFF, 1, INTD, 0 },
Package(){0x0000FFFF, 2, INTA, 0 },
Package(){0x0000FFFF, 3, INTB, 0 },
})
Name(APS6, Package(){
/* PCIe slot - Hooked to PCIe slot 6 */
Package(){0x0000FFFF, 0, 0, 18 },
Package(){0x0000FFFF, 1, 0, 19 },
Package(){0x0000FFFF, 2, 0, 16 },
Package(){0x0000FFFF, 3, 0, 17 },
})
Name(PS7, Package(){
/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
Package(){0x0000FFFF, 0, INTD, 0 },
Package(){0x0000FFFF, 1, INTA, 0 },
Package(){0x0000FFFF, 2, INTB, 0 },
Package(){0x0000FFFF, 3, INTC, 0 },
})
Name(APS7, Package(){
/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
Package(){0x0000FFFF, 0, 0, 19 },
Package(){0x0000FFFF, 1, 0, 16 },
Package(){0x0000FFFF, 2, 0, 17 },
Package(){0x0000FFFF, 3, 0, 18 },
})
Name(PS9, Package(){ Name(PS9, Package(){
/* PCIe slot - Hooked to PCIe slot 9 */ /* PCIe slot - Hooked to PCIe x1 */
Package(){0x0000FFFF, 0, INTD, 0 }, Package(){0x0000FFFF, 0, INTD, 0 },
Package(){0x0000FFFF, 1, INTA, 0 }, Package(){0x0000FFFF, 1, INTA, 0 },
Package(){0x0000FFFF, 2, INTB, 0 }, Package(){0x0000FFFF, 2, INTB, 0 },
@ -271,14 +156,14 @@ Scope(\_SB) {
}) })
Name(APS9, Package(){ Name(APS9, Package(){
/* PCIe slot - Hooked to PCIe slot 9 */ /* PCIe slot - Hooked to PCIe x1 */
Package(){0x0000FFFF, 0, 0, 17 }, Package(){0x0000FFFF, 0, 0, 17 },
Package(){0x0000FFFF, 1, 0, 18 }, Package(){0x0000FFFF, 1, 0, 18 },
Package(){0x0000FFFF, 2, 0, 19 }, Package(){0x0000FFFF, 2, 0, 19 },
Package(){0x0000FFFF, 3, 0, 16 }, Package(){0x0000FFFF, 3, 0, 16 },
}) })
Name(PSa, Package(){ Name(PSa, Package(){
/* PCIe slot - Hooked to PCIe slot 10 */ /* PCIe slot - Hooked to ethernet */
Package(){0x0000FFFF, 0, INTD, 0 }, Package(){0x0000FFFF, 0, INTD, 0 },
Package(){0x0000FFFF, 1, INTA, 0 }, Package(){0x0000FFFF, 1, INTA, 0 },
Package(){0x0000FFFF, 2, INTB, 0 }, Package(){0x0000FFFF, 2, INTB, 0 },

27
src/mainboard/asrock/939a785gmh/devicetree.cb
View File

@ -1,8 +1,9 @@
#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) #Define gppsb_configuration, A=0, B=1, C=2, D=3, E=4(default)
#Define gpp_configuration -> device 9 1x and device a 1x is 3 and device 9 2x is 2
#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
# 1: the system allows a PCIE link to be established on Dev2 or Dev3. # 1: the system allows a PCIE link to be established on Dev2 or Dev3.
#Define gfx_dual_slot, 0: single slot, 1: dual slot #Define gfx_dual_slot, 0: single slot, 1: dual slot (means if GFX slot are two 2 8x slots)
#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable #Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
#Define gfx_tmds, 0: didn't support TMDS, 1: support #Define gfx_tmds, 0: didn't support TMDS, 1: support
#Define gfx_compliance, 0: didn't support compliance, 1: support #Define gfx_compliance, 0: didn't support compliance, 1: support
@ -20,20 +21,20 @@ chip northbridge/amd/amdk8/root_complex
chip southbridge/amd/rs780 chip southbridge/amd/rs780
device pci 0.0 on end # HT 0x9600 device pci 0.0 on end # HT 0x9600
device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 device pci 2.0 on end # PCIE P2P bridge 16x slot
device pci 3.0 on end # PCIE P2P bridge 0x960b device pci 3.0 off end # used in dual slot config
device pci 4.0 on end # PCIE P2P bridge 0x9604 device pci 4.0 off end # GPPSB
device pci 5.0 off end # PCIE P2P bridge 0x9605 device pci 5.0 off end # GPPSB
device pci 6.0 off end # PCIE P2P bridge 0x9606 device pci 6.0 off end # GPPSB
device pci 7.0 off end # PCIE P2P bridge 0x9607 device pci 7.0 off end # GPPSB
device pci 8.0 off end # NB/SB Link P2P bridge device pci 8.0 off end # NB/SB Link P2P bridge
device pci 9.0 on end # device pci 9.0 on end # GPP for x1 slot
device pci a.0 on end # device pci a.0 on end # GPP for internal network adapter
register "gppsb_configuration" = "1" # Configuration B register "gppsb_configuration" = "4" # Configuration ?
register "gpp_configuration" = "3" # Configuration D default register "gpp_configuration" = "3" # Configuration D default
register "port_enable" = "0x6fc" register "port_enable" = "0x60c"
register "gfx_dev2_dev3" = "1" register "gfx_dev2_dev3" = "1"
register "gfx_dual_slot" = "1" register "gfx_dual_slot" = "0"
register "gfx_lane_reversal" = "0" register "gfx_lane_reversal" = "0"
register "gfx_tmds" = "0" register "gfx_tmds" = "0"
register "gfx_compliance" = "0" register "gfx_compliance" = "0"

46
src/mainboard/asrock/939a785gmh/dsdt.asl
View File

@ -1064,10 +1064,6 @@ DefinitionBlock (
Method(_L18) { Method(_L18) {
/* DBGO("\\_GPE\\_L18\n") */ /* DBGO("\\_GPE\\_L18\n") */
Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
} }
@ -1166,46 +1162,7 @@ DefinitionBlock (
} /* end _PRT */ } /* end _PRT */
} /* end PBR2 */ } /* end PBR2 */
/* Dev3 is also an external GFX bridge, not used in Herring */ /* GPP x1 */
Device(PBR4) {
Name(_ADR, 0x00040000)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
If(PMOD){ Return(APS4) } /* APIC mode */
Return (PS4) /* PIC Mode */
} /* end _PRT */
} /* end PBR4 */
Device(PBR5) {
Name(_ADR, 0x00050000)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
If(PMOD){ Return(APS5) } /* APIC mode */
Return (PS5) /* PIC Mode */
} /* end _PRT */
} /* end PBR5 */
Device(PBR6) {
Name(_ADR, 0x00060000)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
If(PMOD){ Return(APS6) } /* APIC mode */
Return (PS6) /* PIC Mode */
} /* end _PRT */
} /* end PBR6 */
/* The onboard EtherNet chip */
Device(PBR7) {
Name(_ADR, 0x00070000)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
If(PMOD){ Return(APS7) } /* APIC mode */
Return (PS7) /* PIC Mode */
} /* end _PRT */
} /* end PBR7 */
/* GPP */
Device(PBR9) { Device(PBR9) {
Name(_ADR, 0x00090000) Name(_ADR, 0x00090000)
Name(_PRW, Package() {0x18, 4}) Name(_PRW, Package() {0x18, 4})
@ -1215,6 +1172,7 @@ DefinitionBlock (
} /* end _PRT */ } /* end _PRT */
} /* end PBR9 */ } /* end PBR9 */
/* ethernet */
Device(PBRa) { Device(PBRa) {
Name(_ADR, 0x000A0000) Name(_ADR, 0x000A0000)
Name(_PRW, Package() {0x18, 4}) Name(_PRW, Package() {0x18, 4})

30
src/mainboard/asrock/939a785gmh/mainboard.c
View File

@ -35,34 +35,12 @@ uint64_t uma_memory_base, uma_memory_size;
void set_pcie_dereset(void); void set_pcie_dereset(void);
void set_pcie_reset(void); void set_pcie_reset(void);
u8 is_dev3_present(void); u8 is_dev3_present(void);
/*
* Mahogany uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to
* pull it up before training the slot.
***/
void set_pcie_dereset() void set_pcie_dereset()
{ {
u16 word;
device_t sm_dev;
/* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
word = pci_read_config16(sm_dev, 0xA8);
word |= (1 << 0) | (1 << 2); /* Set Gpio6,4 as output */
word &= ~((1 << 8) | (1 << 10));
pci_write_config16(sm_dev, 0xA8, word);
} }
void set_pcie_reset() void set_pcie_reset()
{ {
u16 word;
device_t sm_dev;
/* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
word = pci_read_config16(sm_dev, 0xA8);
word &= ~((1 << 0) | (1 << 2)); /* Set Gpio6,4 as output */
word &= ~((1 << 8) | (1 << 10));
pci_write_config16(sm_dev, 0xA8, word);
} }
#if 0 /* not tested yet */ #if 0 /* not tested yet */
@ -103,13 +81,13 @@ u8 is_dev3_present(void)
* enable the dedicated function in mahogany board. * enable the dedicated function in mahogany board.
* This function called early than rs780_enable. * This function called early than rs780_enable.
*************************************************/ *************************************************/
static void mahogany_enable(device_t dev) static void mb_enable(device_t dev)
{ {
/* Leave it for future. */ /* Leave it for future. */
/* struct mainboard_config *mainboard = /* struct mainboard_config *mainboard =
(struct mainboard_config *)dev->chip_info;*/ (struct mainboard_config *)dev->chip_info;*/
printk(BIOS_INFO, "Mainboard MAHOGANY Enable. dev=0x%p\n", dev); printk(BIOS_INFO, "Mainboard 939A785GMH/128M Enable. dev=0x%p\n", dev);
#if (CONFIG_GFXUMA == 1) #if (CONFIG_GFXUMA == 1)
msr_t msr, msr2; msr_t msr, msr2;
@ -170,6 +148,6 @@ int add_mainboard_resources(struct lb_memory *mem)
} }
struct chip_operations mainboard_ops = { struct chip_operations mainboard_ops = {
CHIP_NAME("AMD MAHOGANY Mainboard") CHIP_NAME("Asrock 939A785GMH/128M Mainboard")
.enable_dev = mahogany_enable, .enable_dev = mb_enable,
}; };