gizmosphere/gizmo2: Add the gizmo2 IRQ routing
Change-Id: Ic00790eedd48a2b78620fea329464701cd294cbb Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/7723 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
Dave Frodin
parent
d6aa7cffa3
commit
c7eaf7730d
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@ -2,6 +2,8 @@
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Advanced Micro Devices, Inc.
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* Copyright (C) 2014 Sage Electronic Engineering, LLC
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -25,10 +27,97 @@
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#include <cpu/amd/mtrr.h>
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#include <device/pci_def.h>
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#include <arch/acpi.h>
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#include <southbridge/amd/agesa/hudson/pci_devs.h>
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#include <southbridge/amd/agesa/hudson/amd_pci_int_defs.h>
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#include <southbridge/amd/amd_pci_util.h>
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#include <northbridge/amd/agesa/family16kb/pci_devs.h>
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#include <northbridge/amd/agesa/BiosCallOuts.h>
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#include <cpu/amd/agesa/s3_resume.h>
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#include <northbridge/amd/agesa/agesawrapper.h>
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/***********************************************************
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* These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
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* This table is responsible for physically routing the PIC and
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* IOAPIC IRQs to the different PCI devices on the system. It
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* is read and written via registers 0xC00/0xC01 as an
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* Index/Data pair. These values are chipset and mainboard
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* dependent and should be updated accordingly.
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*
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* These values are used by the PCI configuration space,
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* MP Tables. TODO: Make ACPI use these values too.
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*/
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const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = {
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/* INTA# - INTH# */
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[0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,
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/* Misc-nil,0,1,2, INT from Serial irq */
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[0x08] = 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
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/* SCI, SMBUS0, ASF, HDA, FC, RSVD, PerMon, SD */
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[0x10] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
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/* IMC INT0 - 5 */
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[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
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/* USB Devs 18/19/22 INTA-C */
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[0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,
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/* SATA */
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[0x41] = 0x0F,
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};
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const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = {
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/* INTA# - INTH# */
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[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,
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/* Misc-nil,0,1,2, INT from Serial irq */
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[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
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/* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */
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[0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,
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/* IMC INT0 - 5 */
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[0x20] = 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,
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/* USB Devs 18/19/20/22 INTA-C */
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[0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12,
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/* SATA */
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[0x41] = 0x13
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};
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/*
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* This table defines the index into the picr/intr_data
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* tables for each device. Any enabled device and slot
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* that uses hardware interrupts should have an entry
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* in this table to define its index into the FCH
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* PCI_INTR register 0xC00/0xC01. This index will define
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* the interrupt that it should use. Putting PIRQ_A into
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* the PIN A index for a device will tell that device to
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* use PIC IRQ 10 if it uses PIN A for its hardware INT.
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*/
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static const struct pirq_struct mainboard_pirq_data[] = {
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/* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */
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{GFX_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */
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{ACTL_DEVFN,{PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* Audio: 01.1 */
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{NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* x4 PCIe: 02.1 */
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{NB_PCIE_PORT2_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}}, /* mPCIe: 02.2 */
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{NB_PCIE_PORT3_DEVFN, {PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B}}, /* NIC: 02.3 */
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{NB_PCIE_PORT4_DEVFN, {PIRQ_D, PIRQ_A, PIRQ_B, PIRQ_C}}, /* Edge: 02.4 */
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{NB_PCIE_PORT5_DEVFN, {PIRQ_E, PIRQ_F, PIRQ_G, PIRQ_H}}, /* Edge: 02.5 */
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{XHCI_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* XHCI: 10.0 */
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{SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */
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{OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */
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{EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */
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{OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */
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{EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */
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{SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */
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{HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */
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{SD_DEVFN, {PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SD: 14.7 */
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};
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const u8 *picr_data = mainboard_picr_data;
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const u8 *intr_data = mainboard_intr_data;
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/* PIRQ Setup */
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static void pirq_setup(void)
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{
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pirq_data_ptr = mainboard_pirq_data;
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pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct);
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intr_data_ptr = mainboard_intr_data;
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picr_data_ptr = mainboard_picr_data;
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}
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/**********************************************
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* enable the dedicated function in mainboard.
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**********************************************/
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@ -38,6 +127,9 @@ static void mainboard_enable(device_t dev)
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if (acpi_is_wakeup_s3())
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agesawrapper_fchs3earlyrestore();
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/* Initialize the PIRQ data structures for consumption */
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pirq_setup();
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}
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struct chip_operations mainboard_ops = {
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@ -24,51 +24,16 @@
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#include <arch/ioapic.h>
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#include <string.h>
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#include <stdint.h>
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#include <cpu/amd/amdfam15.h>
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#include <cpu/amd/amdfam16.h>
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#include <arch/cpu.h>
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#include <cpu/x86/lapic.h>
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#include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */
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u8 picr_data[0x54] = {
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0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
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0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x04,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x03,0x04,0x05,0x07
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};
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u8 intr_data[0x54] = {
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0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
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0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x10,0x11,0x12,0x13
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};
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static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length)
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{
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mc->mpc_length += length;
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mc->mpc_entry_count++;
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}
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static void my_smp_write_bus(struct mp_config_table *mc,
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unsigned char id, const char *bustype)
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{
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struct mpc_config_bus *mpc;
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mpc = smp_next_mpc_entry(mc);
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memset(mpc, '\0', sizeof(*mpc));
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mpc->mpc_type = MP_BUS;
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mpc->mpc_busid = id;
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memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
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smp_add_mpc_entry(mc, sizeof(*mpc));
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}
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#include <southbridge/amd/amd_pci_util.h>
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#include <drivers/generic/ioapic/chip.h>
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static void *smp_write_config_table(void *v)
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{
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struct mp_config_table *mc;
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int bus_isa;
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u8 byte;
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/*
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* By the time this function gets called, the IOAPIC registers
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@ -78,147 +43,118 @@ static void *smp_write_config_table(void *v)
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u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
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u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
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/* Intialize the MP_Table */
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mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
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mptable_init(mc, LOCAL_APIC_ADDR);
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memcpy(mc->mpc_oem, "AMD ", 8);
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/*
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* Type 0: Processor Entries:
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* LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
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* CPU Signature (Stepping, Model, Family),
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* Feature Flags
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*/
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smp_write_processors(mc);
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//mptable_write_buses(mc, NULL, &bus_isa);
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my_smp_write_bus(mc, 0, "PCI ");
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my_smp_write_bus(mc, 1, "PCI ");
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bus_isa = 0x02;
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my_smp_write_bus(mc, bus_isa, "ISA ");
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/*
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* Type 1: Bus Entries:
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* Bus ID, Bus Type
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*/
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mptable_write_buses(mc, NULL, &bus_isa);
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/* I/O APICs: APIC ID Version State Address */
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/*
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* Type 2: I/O APICs:
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* APIC ID, Version, APIC Flags:EN, Address
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*/
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smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
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smp_write_ioapic(mc, ioapic_id+1, 0x21, 0xFEC20000);
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/* PIC IRQ routine */
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for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
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outb(byte, 0xC00);
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outb(picr_data[byte], 0xC01);
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}
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/* APIC IRQ routine */
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for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
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outb(byte | 0x80, 0xC00);
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outb(intr_data[byte], 0xC01);
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}
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#if 0
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outb(0x0B, 0xCD6);
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outb(0x02, 0xCD7);
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outb(0x50, 0xCD6);
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outb(0x1F, 0xCD7);
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outb(0x48, 0xCD6);
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outb(0xF2, 0xCD7);
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//outb(0xBE, 0xCD6);
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//outb(0x52, 0xCD7);
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outb(0xED, 0xCD6);
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outb(0x17, 0xCD7);
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*(volatile u8 *) (0xFED80D00 + 0x31) = 2;
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*(volatile u8 *) (0xFED80D00 + 0x32) = 2;
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*(volatile u8 *) (0xFED80D00 + 0x33) = 2;
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*(volatile u8 *) (0xFED80D00 + 0x34) = 2;
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*(volatile u8 *) (0xFED80100 + 0x31) = 0xc8;
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*(volatile u8 *) (0xFED80100 + 0x32) = 0xc8;
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*(volatile u8 *) (0xFED80100 + 0x33) = 0xc8;
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*(volatile u8 *) (0xFED80100 + 0x34) = 0xa0;
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*(volatile u8 *) (0xFED80D00 + 0x6c) = 1;
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*(volatile u8 *) (0xFED80D00 + 0x6E) = 2;
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*(volatile u8 *) (0xFED80D00 + 0x6f) = 2;
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*(volatile u8 *) (0xFED80100 + 0x6c) = 0xa0;
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*(volatile u8 *) (0xFED80100 + 0x6E) = 0xa8;
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*(volatile u8 *) (0xFED80100 + 0x6f) = 0xa0;
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*(volatile u8 *) (0xFED80D00 + 0xA6) = 2;
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*(volatile u8 *) (0xFED80100 + 0xA6) = 0;
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*(volatile u8 *) (0xFED80100 + 0x40) = 0xC8;
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#endif
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/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
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#define IO_LOCAL_INT(type, intr, apicid, pin) \
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smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
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/*
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* Type 3: I/O Interrupt Table Entries:
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* Int Type, Int Polarity, Int Level, Source Bus ID,
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* Source Bus IRQ, Dest APIC ID, Dest PIN#
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*/
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mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
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/* PCI interrupts are level triggered, and are
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* associated with a specific bus/device/function tuple.
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*/
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#define PCI_INT(bus, dev, int_sign, pin) \
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
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#define PCI_INT(bus, dev, fn, pin) \
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
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/* Internal VGA */
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PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
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PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
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/* APU Internal Graphic Device */
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PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
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PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
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/* SMBUS */
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PCI_INT(0x0, 0x14, 0x0, 0x10);
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/* SMBUS / ACPI */
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PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
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/* HD Audio */
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PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
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/* Southbridge HD Audio */
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PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
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/* LPC */
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PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]);
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/* USB */
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PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
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PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
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PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
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PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
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PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
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PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
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PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
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PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
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PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]);
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PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
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PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]);
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PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]);
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PCI_INT(0x0, 0x16, 0x2, intr_data_ptr[PIRQ_EHCI3]);
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PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]);
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/* sata */
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PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
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PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
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/* SATA */
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PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
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/* on board NIC & Slot PCIE. */
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/* on board NIC & Slot PCIE */
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PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]);
|
||||
PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]);
|
||||
|
||||
/* PCI slots */
|
||||
device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
|
||||
if (dev && dev->enabled) {
|
||||
u8 bus_pci = dev->link_list->secondary;
|
||||
/* PCI_SLOT 0. */
|
||||
PCI_INT(bus_pci, 0x5, 0x0, 0x14);
|
||||
PCI_INT(bus_pci, 0x5, 0x1, 0x15);
|
||||
PCI_INT(bus_pci, 0x5, 0x2, 0x16);
|
||||
PCI_INT(bus_pci, 0x5, 0x3, 0x17);
|
||||
/* PCI_SLOT 0 */
|
||||
PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]);
|
||||
PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]);
|
||||
PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]);
|
||||
PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]);
|
||||
|
||||
/* PCI_SLOT 1. */
|
||||
PCI_INT(bus_pci, 0x6, 0x0, 0x15);
|
||||
PCI_INT(bus_pci, 0x6, 0x1, 0x16);
|
||||
PCI_INT(bus_pci, 0x6, 0x2, 0x17);
|
||||
PCI_INT(bus_pci, 0x6, 0x3, 0x14);
|
||||
/* PCI_SLOT 1 */
|
||||
PCI_INT(bus_pci, 0x6, 0x0, intr_data_ptr[PIRQ_F]);
|
||||
PCI_INT(bus_pci, 0x6, 0x1, intr_data_ptr[PIRQ_G]);
|
||||
PCI_INT(bus_pci, 0x6, 0x2, intr_data_ptr[PIRQ_H]);
|
||||
PCI_INT(bus_pci, 0x6, 0x3, intr_data_ptr[PIRQ_E]);
|
||||
|
||||
/* PCI_SLOT 2. */
|
||||
PCI_INT(bus_pci, 0x7, 0x0, 0x16);
|
||||
PCI_INT(bus_pci, 0x7, 0x1, 0x17);
|
||||
PCI_INT(bus_pci, 0x7, 0x2, 0x14);
|
||||
PCI_INT(bus_pci, 0x7, 0x3, 0x15);
|
||||
/* PCI_SLOT 2 */
|
||||
PCI_INT(bus_pci, 0x7, 0x0, intr_data_ptr[PIRQ_G]);
|
||||
PCI_INT(bus_pci, 0x7, 0x1, intr_data_ptr[PIRQ_H]);
|
||||
PCI_INT(bus_pci, 0x7, 0x2, intr_data_ptr[PIRQ_E]);
|
||||
PCI_INT(bus_pci, 0x7, 0x3, intr_data_ptr[PIRQ_F]);
|
||||
|
||||
PCI_INT(bus_pci, 0x0, 0x0, intr_data_ptr[PIRQ_C]);
|
||||
PCI_INT(bus_pci, 0x0, 0x1, intr_data_ptr[PIRQ_D]);
|
||||
PCI_INT(bus_pci, 0x0, 0x2, intr_data_ptr[PIRQ_E]);
|
||||
}
|
||||
|
||||
/* PCIe Lan*/
|
||||
PCI_INT(0x0, 0x06, 0x0, 0x13);
|
||||
PCI_INT(0x0, 0x06, 0x0, intr_data_ptr[PIRQ_D]);
|
||||
|
||||
/* FCH PCIe PortA */
|
||||
PCI_INT(0x0, 0x15, 0x0, 0x10);
|
||||
PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_A]);
|
||||
/* FCH PCIe PortB */
|
||||
PCI_INT(0x0, 0x15, 0x1, 0x11);
|
||||
PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_B]);
|
||||
/* FCH PCIe PortC */
|
||||
PCI_INT(0x0, 0x15, 0x2, 0x12);
|
||||
PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_C]);
|
||||
/* FCH PCIe PortD */
|
||||
PCI_INT(0x0, 0x15, 0x3, 0x13);
|
||||
PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_D]);
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
|
||||
IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
#define IO_LOCAL_INT(type, intr, apicid, pin) \
|
||||
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
|
||||
|
||||
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
|
||||
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
|
|
|
|||
Loading…
Reference in New Issue