MCP55: Cosmetic fixes, switch to u8 et al.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6241 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann
parent
7e2fbd5dd3
commit
c7f0c8feab
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@ -28,33 +28,31 @@
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#include "mcp55.h"
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#define HDA_ICII_REG 0x68
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#define HDA_ICII_BUSY (1 << 0)
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#define HDA_ICII_VALID (1 << 1)
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#define HDA_ICII_BUSY (1 << 0)
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#define HDA_ICII_VALID (1 << 1)
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static int set_bits(u32 port, u32 mask, u32 val)
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{
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u32 reg32;
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int count;
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/* Write (val & mask) to port */
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/* Write (val & mask) to port. */
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val &= mask;
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reg32 = read32(port);
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reg32 &= ~mask;
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reg32 |= val;
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write32(port, reg32);
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/* Wait for readback of register to
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* match what was just written to it
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*/
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/* Wait for readback of register to match what was written to it. */
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count = 50;
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do {
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/* Wait 1ms based on BKDG wait time */
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/* Wait 1ms based on BKDG wait time. */
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mdelay(1);
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reg32 = read32(port);
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reg32 &= mask;
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} while ((reg32 != val) && --count);
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/* Timeout occurred */
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/* Timeout occurred. */
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if (!count)
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return -1;
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return 0;
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@ -64,15 +62,15 @@ static int codec_detect(u32 base)
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{
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u32 reg32;
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/* Set Bit0 to 0 to enter reset state (BAR + 0x8)[0] */
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/* Set bit 0 to 0 to enter reset state (BAR + 0x8)[0]. */
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if (set_bits(base + 0x08, 1, 0) == -1)
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goto no_codec;
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/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
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/* Set bit 0 to 1 to exit reset state (BAR + 0x8)[0]. */
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if (set_bits(base + 0x08, 1, 1) == -1)
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goto no_codec;
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/* Read in Codec location (BAR + 0xe)[2..0]*/
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/* Read in codec location (BAR + 0xe)[2..0]. */
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reg32 = read32(base + 0xe);
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reg32 &= 0x0f;
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if (!reg32)
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@ -81,48 +79,45 @@ static int codec_detect(u32 base)
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return reg32;
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no_codec:
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/* Codec Not found */
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/* Put HDA back in reset (BAR + 0x8) [0] */
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/* Codec not found. */
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/* Put HDA back in reset (BAR + 0x8)[0]. */
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set_bits(base + 0x08, 1, 0);
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printk(BIOS_DEBUG, "Azalia: No codec!\n");
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return 0;
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}
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u32 * cim_verb_data = NULL;
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u32 *cim_verb_data = NULL;
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u32 cim_verb_data_size = 0;
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static u32 find_verb(struct device *dev, u32 viddid, u32 ** verb)
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static u32 find_verb(struct device *dev, u32 viddid, u32 **verb)
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{
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int idx=0;
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int idx = 0;
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while (idx < (cim_verb_data_size / sizeof(u32))) {
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u32 verb_size = 4 * cim_verb_data[idx+2]; // in u32
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u32 verb_size = 4 * cim_verb_data[idx + 2]; /* in u32 */
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if (cim_verb_data[idx] != viddid) {
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idx += verb_size + 3; // skip verb + header
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idx += verb_size + 3; /* Skip verb + header. */
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continue;
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}
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*verb = &cim_verb_data[idx+3];
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*verb = &cim_verb_data[idx + 3];
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return verb_size;
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}
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/* Not all codecs need to load another verb */
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/* Not all codecs need to load another verb. */
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return 0;
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}
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/**
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* Wait 50usec for the codec to indicate it is ready
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* no response would imply that the codec is non-operative
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* Wait 50usec for the codec to indicate it is ready.
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* No response would imply that the codec is non-operative.
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*/
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static int wait_for_ready(u32 base)
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{
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/* Use a 50 usec timeout - the Linux kernel uses the
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* same duration */
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/* Use a 50 usec timeout - the Linux kernel uses the same duration. */
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int timeout = 50;
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while(timeout--) {
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u32 reg32 = read32(base + HDA_ICII_REG);
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while (timeout--) {
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u32 reg32 = read32(base + HDA_ICII_REG);
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if (!(reg32 & HDA_ICII_BUSY))
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return 0;
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udelay(1);
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@ -132,25 +127,21 @@ static int wait_for_ready(u32 base)
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}
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/**
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* Wait 50usec for the codec to indicate that it accepted
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* the previous command. No response would imply that the code
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* is non-operative
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* Wait 50usec for the codec to indicate that it accepted the previous command.
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* No response would imply that the code is non-operative.
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*/
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static int wait_for_valid(u32 base)
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{
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u32 reg32;
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/* Send the verb to the codec */
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/* Send the verb to the codec. */
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reg32 = read32(base + 0x68);
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reg32 |= (1 << 0) | (1 << 1);
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write32(base + 0x68, reg32);
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/* Use a 50 usec timeout - the Linux kernel uses the
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* same duration */
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/* Use a 50 usec timeout - the Linux kernel uses the same duration. */
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int timeout = 50;
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while(timeout--) {
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while (timeout--) {
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reg32 = read32(base + HDA_ICII_REG);
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if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
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HDA_ICII_VALID)
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@ -163,9 +154,8 @@ static int wait_for_valid(u32 base)
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static void codec_init(struct device *dev, u32 base, int addr)
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{
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u32 reg32;
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u32 reg32, verb_size;
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u32 *verb;
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u32 verb_size;
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int i;
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printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr);
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@ -216,44 +206,44 @@ static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
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static void azalia_init(struct device *dev)
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{
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u32 base;
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u32 base, codec_mask, reg32;
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struct resource *res;
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u32 codec_mask;
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u8 reg8;
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u32 reg32;
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/* Set Bus Master */
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/* Set bus master. */
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reg32 = pci_read_config32(dev, PCI_COMMAND);
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pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
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pci_write_config8(dev, 0x3c, 0x0a); // unused?
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pci_write_config8(dev, 0x3c, 0x0a); // TODO: Unused?
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reg8 = pci_read_config8(dev, 0x40);
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reg8 |= (1 << 3); // Clear Clock Detect Bit
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reg8 |= (1 << 3); /* Clear Clock Detect bit. */
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pci_write_config8(dev, 0x40, reg8);
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reg8 &= ~(1 << 3); // Keep CLKDETCLR from clearing the bit over and over
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reg8 &= ~(1 << 3); /* Keep CLKDETCLR from clearing the bit over and over. */
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pci_write_config8(dev, 0x40, reg8);
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reg8 |= (1 << 2); // Enable clock detection
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reg8 |= (1 << 2); /* Enable clock detection. */
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pci_write_config8(dev, 0x40, reg8);
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mdelay(1);
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reg8 = pci_read_config8(dev, 0x40);
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printk(BIOS_DEBUG, "Azalia: codec type: %s\n", (reg8 & (1 << 1))?"Azalia":"AC97");
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printk(BIOS_DEBUG, "Azalia: codec type: %s\n",
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(reg8 & (1 << 1)) ? "Azalia" : "AC97");
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//
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reg8 = pci_read_config8(dev, 0x40); // Audio Control
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reg8 |= 1; // Select Azalia mode. This needs to be controlled via devicetree.cb
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reg8 = pci_read_config8(dev, 0x40); /* Audio control */
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reg8 |= 1; /* Select Azalia mode. TODO: Control via devicetree.cb. */
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pci_write_config8(dev, 0x40, reg8);
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reg8 = pci_read_config8(dev, 0x4d); // Docking Status
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reg8 &= ~(1 << 7); // Docking not supported
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reg8 = pci_read_config8(dev, 0x4d); /* Docking status. */
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reg8 &= ~(1 << 7); /* Docking not supported. */
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pci_write_config8(dev, 0x4d, reg8);
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res = find_resource(dev, 0x10);
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if (!res)
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return;
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// NOTE this will break as soon as the Azalia get's a bar above
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// 4G. Is there anything we can do about it?
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/*
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* NOTE: This will break as soon as the Azalia gets a BAR above
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* 4G. Is there anything we can do about it?
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*/
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base = (u32)res->base;
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printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
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codec_mask = codec_detect(base);
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@ -276,7 +266,7 @@ static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device)
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}
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static struct pci_operations azalia_pci_ops = {
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.set_subsystem = azalia_set_subsystem,
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.set_subsystem = azalia_set_subsystem,
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};
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static struct device_operations azalia_ops = {
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@ -294,4 +284,3 @@ static const struct pci_driver azalia __pci_driver = {
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.vendor = PCI_VENDOR_ID_NVIDIA,
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.device = PCI_DEVICE_ID_NVIDIA_MCP55_AZA,
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};
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@ -28,28 +28,28 @@
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static void mcp55_enable_rom(void)
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{
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uint8_t byte;
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uint16_t word;
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u8 byte;
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u16 word;
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device_t addr;
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/* Enable 4MB rom access at 0xFFC00000 - 0xFFFFFFFF */
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/* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */
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#if 0
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/* default MCP55 LPC single */
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/* Default MCP55 LPC single */
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addr = pci_locate_device(PCI_ID(0x10de, 0x0367), 0);
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#else
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// addr = pci_locate_device(PCI_ID(0x10de, 0x0360), 0);
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addr = PCI_DEV(0, (MCP55_DEVN_BASE+1), 0);
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addr = PCI_DEV(0, (MCP55_DEVN_BASE + 1), 0);
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#endif
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/* Set the 4MB enable bit bit */
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/* Set the 15MB enable bits. */
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byte = pci_read_config8(addr, 0x88);
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byte |= 0xff; //256K
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byte |= 0xff; /* 256K */
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pci_write_config8(addr, 0x88, byte);
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byte = pci_read_config8(addr, 0x8c);
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byte |= 0xff; //1M
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byte |= 0xff; /* 1M */
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pci_write_config8(addr, 0x8c, byte);
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word = pci_read_config16(addr, 0x90);
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word |= 0x7fff; //15M
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word |= 0x7fff; /* 15M */
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pci_write_config16(addr, 0x90, word);
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}
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@ -19,8 +19,8 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef MCP55_CHIP_H
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#define MCP55_CHIP_H
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#ifndef SOUTHBRIDGE_NVIDIA_MCP55_CHIP_H
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#define SOUTHBRIDGE_NVIDIA_MCP55_CHIP_H
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#include <device/device.h>
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@ -36,4 +36,4 @@ struct southbridge_nvidia_mcp55_config
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struct chip_operations;
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extern struct chip_operations southbridge_nvidia_mcp55_ops;
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#endif /* MCP55_CHIP_H */
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#endif
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@ -26,14 +26,11 @@ static unsigned get_sbdn(unsigned bus)
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{
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device_t dev;
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/* Find the device.
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*/
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dev = pci_locate_device_on_bus(
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PCI_ID(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_MCP55_HT),
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bus);
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return (dev>>15) & 0x1f;
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/* Find the device. */
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dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
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PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
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return (dev >> 15) & 0x1f;
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}
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void soft_reset(void)
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@ -55,7 +52,6 @@ void hard_reset(void)
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void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
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{
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/* default value for mcp55 is good */
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/* set VFSMAF ( VID/FID System Management Action Field) to 2 */
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/* The default value for MCP55 is good. */
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/* Set VFSMAF (VID/FID System Management Action Field) to 2. */
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}
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@ -19,30 +19,29 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifdef UNUSED_CODE
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int set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned vendorid, unsigned val);
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int set_ht_link_buffer_counts_chain(u8 ht_c_num, unsigned vendorid, unsigned val);
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static int set_ht_link_mcp55(uint8_t ht_c_num)
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static int set_ht_link_mcp55(u8 ht_c_num)
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{
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unsigned vendorid = 0x10de;
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unsigned val = 0x01610109;
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/* Nvidia mcp55 hardcode, hw can not set it automatically */
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/* NVIDIA MCP55 hardcode, hardware can not set it automatically. */
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return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val);
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}
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static void setup_ss_table(unsigned index, unsigned where, unsigned control, const unsigned int *register_values, int max)
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static void setup_ss_table(unsigned index, unsigned where, unsigned control,
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const unsigned int *register_values, int max)
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{
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int i;
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unsigned val;
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val = inl(control);
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val &= 0xfffffffe;
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outl(val, control);
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outl(0, index); //index
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for(i = 0; i < max; i++) {
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outl(0, index); /* Index */
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for (i = 0; i < max; i++) {
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unsigned long reg;
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reg = register_values[i];
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outl(reg, where);
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@ -51,7 +50,6 @@ static void setup_ss_table(unsigned index, unsigned where, unsigned control, con
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val = inl(control);
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val |= 1;
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outl(val, control);
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}
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#endif
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@ -68,17 +66,18 @@ static void setup_ss_table(unsigned index, unsigned where, unsigned control, con
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#define ACPICTRL_REG_POS 0x60
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/*
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16 1 1 1 1 8 :0
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16 0 4 0 0 8 :1
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16 0 4 2 2 4 :2
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4 4 4 4 4 8 :3
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8 8 4 0 0 8 :4
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8 0 4 4 4 8 :5
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* 16 1 1 1 1 8 :0
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* 16 0 4 0 0 8 :1
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* 16 0 4 2 2 4 :2
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* 4 4 4 4 4 8 :3
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* 8 8 4 0 0 8 :4
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* 8 0 4 4 4 8 :5
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*/
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#define MCP55_CHIP_REV 3
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#define MCP55_CHIP_REV 3
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static void mcp55_early_set_port(unsigned mcp55_num, unsigned *busn, unsigned *devn, unsigned *io_base)
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static void mcp55_early_set_port(unsigned mcp55_num, unsigned *busn,
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unsigned *devn, unsigned *io_base)
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{
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static const unsigned int ctrl_devport_conf[] = {
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@ -88,16 +87,16 @@ static void mcp55_early_set_port(unsigned mcp55_num, unsigned *busn, unsigned *d
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};
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int j;
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for(j = 0; j < mcp55_num; j++ ) {
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for (j = 0; j < mcp55_num; j++ ) {
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setup_resource_map_offset(ctrl_devport_conf,
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ARRAY_SIZE(ctrl_devport_conf),
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PCI_DEV(busn[j], devn[j], 0) , io_base[j]);
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}
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}
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static void mcp55_early_clear_port(unsigned mcp55_num, unsigned *busn, unsigned *devn, unsigned *io_base)
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static void mcp55_early_clear_port(unsigned mcp55_num, unsigned *busn,
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unsigned *devn, unsigned *io_base)
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{
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static const unsigned int ctrl_devport_conf_clear[] = {
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PCI_ADDR(0, 1, 1, ANACTRL_REG_POS), ~(0x0000ff00), 0,
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PCI_ADDR(0, 1, 1, SYSCTRL_REG_POS), ~(0x0000ff00), 0,
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@ -105,58 +104,56 @@ static void mcp55_early_clear_port(unsigned mcp55_num, unsigned *busn, unsigned
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};
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int j;
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for(j = 0; j < mcp55_num; j++ ) {
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for (j = 0; j < mcp55_num; j++ ) {
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setup_resource_map_offset(ctrl_devport_conf_clear,
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ARRAY_SIZE(ctrl_devport_conf_clear),
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PCI_DEV(busn[j], devn[j], 0) , io_base[j]);
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
static void mcp55_early_pcie_setup(unsigned busnx, unsigned devnx, unsigned anactrl_io_base, unsigned pci_e_x)
|
||||
static void mcp55_early_pcie_setup(unsigned busnx, unsigned devnx,
|
||||
unsigned anactrl_io_base, unsigned pci_e_x)
|
||||
{
|
||||
uint32_t tgio_ctrl;
|
||||
uint32_t pll_ctrl;
|
||||
uint32_t dword;
|
||||
u32 tgio_ctrl, pll_ctrl, dword;
|
||||
int i;
|
||||
device_t dev;
|
||||
dev = PCI_DEV(busnx, devnx+1, 1);
|
||||
|
||||
dev = PCI_DEV(busnx, devnx + 1, 1);
|
||||
|
||||
dword = pci_read_config32(dev, 0xe4);
|
||||
dword |= 0x3f0; // disable it at first
|
||||
dword |= 0x3f0; /* Disable it at first. */
|
||||
pci_write_config32(dev, 0xe4, dword);
|
||||
|
||||
for(i=0; i<3; i++) {
|
||||
for (i = 0; i < 3; i++) {
|
||||
tgio_ctrl = inl(anactrl_io_base + 0xcc);
|
||||
tgio_ctrl &= ~(3<<9);
|
||||
tgio_ctrl |= (i<<9);
|
||||
tgio_ctrl &= ~(3 << 9);
|
||||
tgio_ctrl |= (i << 9);
|
||||
outl(tgio_ctrl, anactrl_io_base + 0xcc);
|
||||
pll_ctrl = inl(anactrl_io_base + 0x30);
|
||||
pll_ctrl |= (1<<31);
|
||||
pll_ctrl |= (1 << 31);
|
||||
outl(pll_ctrl, anactrl_io_base + 0x30);
|
||||
do {
|
||||
pll_ctrl = inl(anactrl_io_base + 0x30);
|
||||
} while (!(pll_ctrl & 1));
|
||||
}
|
||||
tgio_ctrl = inl(anactrl_io_base + 0xcc);
|
||||
tgio_ctrl &= ~((7<<4)|(1<<8));
|
||||
tgio_ctrl |= (pci_e_x<<4)|(1<<8);
|
||||
tgio_ctrl &= ~((7 << 4) | (1 << 8));
|
||||
tgio_ctrl |= (pci_e_x << 4) | (1 << 8);
|
||||
outl(tgio_ctrl, anactrl_io_base + 0xcc);
|
||||
|
||||
// wait 100us
|
||||
udelay(100);
|
||||
udelay(100); /* Wait 100us. */
|
||||
|
||||
dword = pci_read_config32(dev, 0xe4);
|
||||
dword &= ~(0x3f0); // enable
|
||||
dword &= ~(0x3f0); /* Enable. */
|
||||
pci_write_config32(dev, 0xe4, dword);
|
||||
|
||||
// need to wait 100ms
|
||||
mdelay(100);
|
||||
mdelay(100); /* Need to wait 100ms. */
|
||||
}
|
||||
|
||||
static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, unsigned *devn, unsigned *io_base, unsigned *pci_e_x)
|
||||
static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn,
|
||||
unsigned *devn, unsigned *io_base,
|
||||
unsigned *pci_e_x)
|
||||
{
|
||||
|
||||
static const unsigned int ctrl_conf_1[] = {
|
||||
RES_PORT_IO_32, ACPICTRL_IO_BASE + 0x10, 0x0007ffff, 0xff78000,
|
||||
RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xa4, 0xffedffff, 0x0012000,
|
||||
|
|
@ -199,11 +196,11 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, unsigned *devn
|
|||
|
||||
RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x40), 0x00000000, 0xCB8410DE,
|
||||
RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x68), 0xFFFFFF00, 0x000000FF,
|
||||
RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xF8), 0xFFFFFFBF, 0x00000040,//Enable bridge mode
|
||||
RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xF8), 0xFFFFFFBF, 0x00000040, /* Enable bridge mode. */
|
||||
|
||||
RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x40), 0x00000000, 0xCB8410DE,
|
||||
RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x68), 0xFFFFFF00, 0x000000FF,
|
||||
RES_PCI_IO, PCI_ADDR(0, 9, 0, 0xF8), 0xFFFFFFBF, 0x00000040,//Enable bridge mode
|
||||
RES_PCI_IO, PCI_ADDR(0, 9, 0, 0xF8), 0xFFFFFFBF, 0x00000040, /* Enable bridge mode. */
|
||||
};
|
||||
|
||||
static const unsigned int ctrl_conf_1_1[] = {
|
||||
|
|
@ -218,7 +215,6 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, unsigned *devn
|
|||
RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xE0), 0xF0FFFFFF, 0x03000000,
|
||||
};
|
||||
|
||||
|
||||
static const unsigned int ctrl_conf_mcp55_only[] = {
|
||||
RES_PCI_IO, PCI_ADDR(0, 1, 1, 0x40), 0x00000000, 0xCB8410DE,
|
||||
RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE0), 0xFFFFFEFF, 0x00000000,
|
||||
|
|
@ -251,33 +247,30 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, unsigned *devn
|
|||
#if CONFIG_MCP55_USE_AZA
|
||||
RES_PCI_IO, PCI_ADDR(0, 6, 1, 0x40), 0x00000000, 0xCB8410DE,
|
||||
|
||||
// RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE4), ~(1<<14), 1<<14,
|
||||
// RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE4), ~(1 << 14), (1 << 14),
|
||||
#endif
|
||||
// play a while with GPIO in MCP55
|
||||
|
||||
#ifdef MCP55_MB_SETUP
|
||||
/* Play a while with GPIO in MCP55. */
|
||||
MCP55_MB_SETUP
|
||||
#endif
|
||||
|
||||
#if CONFIG_MCP55_USE_AZA
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 21, ~(3<<2), (2<<2),
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 22, ~(3<<2), (2<<2),
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 46, ~(3<<2), (2<<2),
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 21, ~(3 << 2), (2 << 2),
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 22, ~(3 << 2), (2 << 2),
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 46, ~(3 << 2), (2 << 2),
|
||||
#endif
|
||||
|
||||
|
||||
};
|
||||
|
||||
static const unsigned int ctrl_conf_master_only[] = {
|
||||
|
||||
RES_PORT_IO_32, ACPICTRL_IO_BASE + 0x80, 0xEFFFFFF, 0x01000000,
|
||||
|
||||
//Master MCP55 ????YHLU
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 0, ~(3<<2), (0<<2),
|
||||
|
||||
/* Master MCP55???? YHLU */
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 0, ~(3 << 2), (0 << 2),
|
||||
};
|
||||
|
||||
static const unsigned int ctrl_conf_2[] = {
|
||||
/* I didn't put pcie related stuff here */
|
||||
/* I didn't put PCI-E related stuff here. */
|
||||
|
||||
RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x74), 0xFFFFF00F, 0x000009D0,
|
||||
RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x74), 0xFFFF7FFF, 0x00008000,
|
||||
|
|
@ -286,117 +279,129 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, unsigned *devn
|
|||
|
||||
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x60, 0xFFFFFF00, 0x00000012,
|
||||
|
||||
|
||||
#if CONFIG_MCP55_USE_NIC
|
||||
RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xe4), ~((1<<22)|(1<<20)), (1<<22)|(1<<20),
|
||||
RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xe4), ~((1 << 22) | (1 << 20)), (1 << 22) | (1 << 20),
|
||||
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff), ((0<<4)|(1<<2)|(0<<0)),
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff), ((0<<4)|(1<<2)|(1<<0)),
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)),
|
||||
#endif
|
||||
|
||||
};
|
||||
|
||||
|
||||
int j, i;
|
||||
|
||||
for(j=0; j<mcp55_num; j++) {
|
||||
mcp55_early_pcie_setup(busn[j], devn[j], io_base[j] + ANACTRL_IO_BASE, pci_e_x[j]);
|
||||
for (j = 0; j < mcp55_num; j++) {
|
||||
mcp55_early_pcie_setup(busn[j], devn[j],
|
||||
io_base[j] + ANACTRL_IO_BASE, pci_e_x[j]);
|
||||
|
||||
setup_resource_map_x_offset(ctrl_conf_1, ARRAY_SIZE(ctrl_conf_1),
|
||||
setup_resource_map_x_offset(ctrl_conf_1,
|
||||
ARRAY_SIZE(ctrl_conf_1),
|
||||
PCI_DEV(busn[j], devn[j], 0), io_base[j]);
|
||||
for(i=0; i<3; i++) { // three SATA
|
||||
setup_resource_map_x_offset(ctrl_conf_1_1, ARRAY_SIZE(ctrl_conf_1_1),
|
||||
|
||||
for (i = 0; i < 3; i++) { /* Three SATA */
|
||||
setup_resource_map_x_offset(ctrl_conf_1_1,
|
||||
ARRAY_SIZE(ctrl_conf_1_1),
|
||||
PCI_DEV(busn[j], devn[j], i), io_base[j]);
|
||||
}
|
||||
if(busn[j] == 0) {
|
||||
setup_resource_map_x_offset(ctrl_conf_mcp55_only, ARRAY_SIZE(ctrl_conf_mcp55_only),
|
||||
|
||||
if (busn[j] == 0) {
|
||||
setup_resource_map_x_offset(ctrl_conf_mcp55_only,
|
||||
ARRAY_SIZE(ctrl_conf_mcp55_only),
|
||||
PCI_DEV(busn[j], devn[j], 0), io_base[j]);
|
||||
}
|
||||
|
||||
if( (busn[j] == 0) && (mcp55_num>1) ) {
|
||||
setup_resource_map_x_offset(ctrl_conf_master_only, ARRAY_SIZE(ctrl_conf_master_only),
|
||||
if ((busn[j] == 0) && (mcp55_num>1)) {
|
||||
setup_resource_map_x_offset(ctrl_conf_master_only,
|
||||
ARRAY_SIZE(ctrl_conf_master_only),
|
||||
PCI_DEV(busn[j], devn[j], 0), io_base[j]);
|
||||
}
|
||||
|
||||
setup_resource_map_x_offset(ctrl_conf_2, ARRAY_SIZE(ctrl_conf_2),
|
||||
setup_resource_map_x_offset(ctrl_conf_2,
|
||||
ARRAY_SIZE(ctrl_conf_2),
|
||||
PCI_DEV(busn[j], devn[j], 0), io_base[j]);
|
||||
|
||||
}
|
||||
|
||||
#if 0
|
||||
for(j=0; j< mcp55_num; j++) {
|
||||
for (j = 0; j < mcp55_num; j++) {
|
||||
// PCI-E (XSPLL) SS table 0x40, x044, 0x48
|
||||
// SATA (SPPLL) SS table 0xb0, 0xb4, 0xb8
|
||||
// CPU (PPLL) SS table 0xc0, 0xc4, 0xc8
|
||||
setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0x40, io_base[j] + ANACTRL_IO_BASE+0x44,
|
||||
io_base[j] + ANACTRL_IO_BASE+0x48, pcie_ss_tbl, 64);
|
||||
setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0xb0, io_base[j] + ANACTRL_IO_BASE+0xb4,
|
||||
io_base[j] + ANACTRL_IO_BASE+0xb8, sata_ss_tbl, 64);
|
||||
setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0xc0, io_base[j] + ANACTRL_IO_BASE+0xc4,
|
||||
io_base[j] + ANACTRL_IO_BASE+0xc8, cpu_ss_tbl, 64);
|
||||
setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0x40,
|
||||
io_base[j] + ANACTRL_IO_BASE + 0x44,
|
||||
io_base[j] + ANACTRL_IO_BASE + 0x48, pcie_ss_tbl, 64);
|
||||
setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0xb0,
|
||||
io_base[j] + ANACTRL_IO_BASE + 0xb4,
|
||||
io_base[j] + ANACTRL_IO_BASE + 0xb8, sata_ss_tbl, 64);
|
||||
setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0xc0,
|
||||
io_base[j] + ANACTRL_IO_BASE + 0xc4,
|
||||
io_base[j] + ANACTRL_IO_BASE + 0xc8, cpu_ss_tbl, 64);
|
||||
}
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
#ifndef HT_CHAIN_NUM_MAX
|
||||
|
||||
#define HT_CHAIN_NUM_MAX 4
|
||||
#define HT_CHAIN_BUSN_D 0x40
|
||||
#define HT_CHAIN_BUSN_D 0x40
|
||||
#define HT_CHAIN_IOBASE_D 0x4000
|
||||
|
||||
#endif
|
||||
|
||||
static int mcp55_early_setup_x(void)
|
||||
{
|
||||
/*find out how many mcp55 we have */
|
||||
/* Find out how many MCP55 we have. */
|
||||
unsigned busn[HT_CHAIN_NUM_MAX] = {0};
|
||||
unsigned devn[HT_CHAIN_NUM_MAX] = {0};
|
||||
unsigned io_base[HT_CHAIN_NUM_MAX] = {0};
|
||||
/*
|
||||
FIXME: May have problem if there is different MCP55 HTX card with different PCI_E lane allocation
|
||||
Need to use same trick about pci1234 to verify node/link connection
|
||||
*/
|
||||
unsigned pci_e_x[HT_CHAIN_NUM_MAX] = {CONFIG_MCP55_PCI_E_X_0, CONFIG_MCP55_PCI_E_X_1, CONFIG_MCP55_PCI_E_X_2, CONFIG_MCP55_PCI_E_X_3 };
|
||||
int mcp55_num = 0;
|
||||
unsigned busnx;
|
||||
unsigned devnx;
|
||||
int ht_c_index;
|
||||
|
||||
/* FIXME: multi pci segment handling */
|
||||
/*
|
||||
* FIXME: May have problem if there is different MCP55 HTX card with
|
||||
* different PCI_E lane allocation. Need to use same trick about
|
||||
* pci1234 to verify node/link connection.
|
||||
*/
|
||||
unsigned pci_e_x[HT_CHAIN_NUM_MAX] = {
|
||||
CONFIG_MCP55_PCI_E_X_0, CONFIG_MCP55_PCI_E_X_1,
|
||||
CONFIG_MCP55_PCI_E_X_2, CONFIG_MCP55_PCI_E_X_3,
|
||||
};
|
||||
int mcp55_num = 0, ht_c_index;
|
||||
unsigned busnx, devnx;
|
||||
|
||||
/* FIXME: Multi PCI segment handling. */
|
||||
|
||||
/* Any system that only have IO55 without MCP55? */
|
||||
for(ht_c_index = 0; ht_c_index<HT_CHAIN_NUM_MAX; ht_c_index++) {
|
||||
for (ht_c_index = 0; ht_c_index < HT_CHAIN_NUM_MAX; ht_c_index++) {
|
||||
busnx = ht_c_index * HT_CHAIN_BUSN_D;
|
||||
for(devnx=0;devnx<0x20;devnx++) {
|
||||
uint32_t id;
|
||||
for (devnx = 0; devnx < 0x20; devnx++) {
|
||||
u32 id;
|
||||
device_t dev;
|
||||
dev = PCI_DEV(busnx, devnx, 0);
|
||||
id = pci_read_config32(dev, PCI_VENDOR_ID);
|
||||
if(id == 0x036910de) {
|
||||
busn[mcp55_num] = busnx;
|
||||
devn[mcp55_num] = devnx;
|
||||
io_base[mcp55_num] = ht_c_index * HT_CHAIN_IOBASE_D; // we may have ht chain other than MCP55
|
||||
|
||||
/* We may have HT chain other than MCP55. */
|
||||
io_base[mcp55_num]
|
||||
= ht_c_index * HT_CHAIN_IOBASE_D;
|
||||
|
||||
mcp55_num++;
|
||||
if(mcp55_num == CONFIG_MCP55_NUM) goto out;
|
||||
break; // only one MCP55 on one chain
|
||||
if (mcp55_num == CONFIG_MCP55_NUM)
|
||||
goto out;
|
||||
break; /* Only one MCP55 on one chain. */
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
out:
|
||||
print_debug("mcp55_num:"); print_debug_hex8(mcp55_num); print_debug("\n");
|
||||
print_debug("mcp55_num:");
|
||||
print_debug_hex8(mcp55_num);
|
||||
print_debug("\n");
|
||||
|
||||
mcp55_early_set_port(mcp55_num, busn, devn, io_base);
|
||||
mcp55_early_setup(mcp55_num, busn, devn, io_base, pci_e_x);
|
||||
|
||||
mcp55_early_clear_port(mcp55_num, busn, devn, io_base);
|
||||
|
||||
// set_ht_link_mcp55(HT_CHAIN_NUM_MAX);
|
||||
// set_ht_link_mcp55(HT_CHAIN_NUM_MAX);
|
||||
|
||||
return 0;
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -85,6 +85,7 @@ static const unsigned int pcie_ss_tbl[] = {
|
|||
0x0C5042040,
|
||||
0x0C5042040,
|
||||
};
|
||||
|
||||
static const unsigned int sata_ss_tbl[] = {
|
||||
0x0c9044042,
|
||||
0x0c9044042,
|
||||
|
|
@ -218,5 +219,3 @@ static const unsigned int cpu_ss_tbl[] = {
|
|||
0x0C5039037,
|
||||
0x0C5039037,
|
||||
};
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -24,8 +24,8 @@
|
|||
#include "smbus.h"
|
||||
|
||||
#define SMBUS0_IO_BASE 0x1000
|
||||
#define SMBUS1_IO_BASE (0x1000+(1<<8))
|
||||
/*SIZE 0x40 */
|
||||
#define SMBUS1_IO_BASE (0x1000 + (1 << 8))
|
||||
/* Size: 0x40 */
|
||||
|
||||
static void enable_smbus(void)
|
||||
{
|
||||
|
|
@ -35,12 +35,14 @@ static void enable_smbus(void)
|
|||
if (dev == PCI_DEV_INVALID)
|
||||
die("SMBus controller not found\n");
|
||||
|
||||
/* set smbus iobase */
|
||||
/* Set SMBus I/O base. */
|
||||
pci_write_config32(dev, 0x20, SMBUS0_IO_BASE | 1);
|
||||
pci_write_config32(dev, 0x24, SMBUS1_IO_BASE | 1);
|
||||
/* Set smbus iospace enable */
|
||||
|
||||
/* Set SMBus I/O space enable. */
|
||||
pci_write_config16(dev, 0x4, 0x01);
|
||||
/* clear any lingering errors, so the transaction will run */
|
||||
|
||||
/* Clear any lingering errors, so the transaction will run. */
|
||||
outb(inb(SMBUS0_IO_BASE + SMBHSTSTAT), SMBUS0_IO_BASE + SMBHSTSTAT);
|
||||
outb(inb(SMBUS1_IO_BASE + SMBHSTSTAT), SMBUS1_IO_BASE + SMBHSTSTAT);
|
||||
}
|
||||
|
|
@ -60,28 +62,34 @@ static inline int smbus_read_byte(unsigned device, unsigned address)
|
|||
return do_smbus_read_byte(SMBUS0_IO_BASE, device, address);
|
||||
}
|
||||
|
||||
static inline int smbus_write_byte(unsigned device, unsigned address, unsigned char val)
|
||||
static inline int smbus_write_byte(unsigned device, unsigned address,
|
||||
unsigned char val)
|
||||
{
|
||||
return do_smbus_write_byte(SMBUS0_IO_BASE, device, address, val);
|
||||
}
|
||||
|
||||
static inline int smbusx_recv_byte(unsigned smb_index, unsigned device)
|
||||
{
|
||||
return do_smbus_recv_byte(SMBUS0_IO_BASE + (smb_index<<8), device);
|
||||
return do_smbus_recv_byte(SMBUS0_IO_BASE + (smb_index << 8), device);
|
||||
}
|
||||
|
||||
static inline int smbusx_send_byte(unsigned smb_index, unsigned device, unsigned char val)
|
||||
static inline int smbusx_send_byte(unsigned smb_index, unsigned device,
|
||||
unsigned char val)
|
||||
{
|
||||
return do_smbus_send_byte(SMBUS0_IO_BASE + (smb_index<<8), device, val);
|
||||
return do_smbus_send_byte(SMBUS0_IO_BASE + (smb_index << 8),
|
||||
device, val);
|
||||
}
|
||||
|
||||
static inline int smbusx_read_byte(unsigned smb_index, unsigned device, unsigned address)
|
||||
static inline int smbusx_read_byte(unsigned smb_index, unsigned device,
|
||||
unsigned address)
|
||||
{
|
||||
return do_smbus_read_byte(SMBUS0_IO_BASE + (smb_index<<8), device, address);
|
||||
return do_smbus_read_byte(SMBUS0_IO_BASE + (smb_index << 8),
|
||||
device, address);
|
||||
}
|
||||
|
||||
static inline int smbusx_write_byte(unsigned smb_index, unsigned device, unsigned address, unsigned char val)
|
||||
static inline int smbusx_write_byte(unsigned smb_index, unsigned device,
|
||||
unsigned address, unsigned char val)
|
||||
{
|
||||
return do_smbus_write_byte(SMBUS0_IO_BASE + (smb_index<<8), device, address, val);
|
||||
return do_smbus_write_byte(SMBUS0_IO_BASE + (smb_index << 8),
|
||||
device, address, val);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -28,13 +28,13 @@
|
|||
#include <device/pci_ops.h>
|
||||
#include "mcp55.h"
|
||||
|
||||
static struct device_operations ht_ops = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = 0,
|
||||
.scan_bus = 0,
|
||||
.ops_pci = &mcp55_pci_ops,
|
||||
static struct device_operations ht_ops = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = 0,
|
||||
.scan_bus = 0,
|
||||
.ops_pci = &mcp55_pci_ops,
|
||||
};
|
||||
|
||||
static const struct pci_driver ht_driver __pci_driver = {
|
||||
|
|
@ -42,4 +42,3 @@ static const struct pci_driver ht_driver __pci_driver = {
|
|||
.vendor = PCI_VENDOR_ID_NVIDIA,
|
||||
.device = PCI_DEVICE_ID_NVIDIA_MCP55_HT,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -31,33 +31,31 @@
|
|||
static void ide_init(struct device *dev)
|
||||
{
|
||||
struct southbridge_nvidia_mcp55_config *conf;
|
||||
/* Enable ide devices so the linux ide driver will work */
|
||||
uint32_t dword;
|
||||
uint16_t word;
|
||||
uint8_t byte;
|
||||
u32 dword;
|
||||
u16 word;
|
||||
u8 byte;
|
||||
conf = dev->chip_info;
|
||||
|
||||
word = pci_read_config16(dev, 0x50);
|
||||
/* Ensure prefetch is disabled */
|
||||
/* Ensure prefetch is disabled. */
|
||||
word &= ~((1 << 15) | (1 << 13));
|
||||
if (conf->ide1_enable) {
|
||||
/* Enable secondary ide interface */
|
||||
word |= (1<<0);
|
||||
/* Enable secondary IDE interface. */
|
||||
word |= (1 << 0);
|
||||
printk(BIOS_DEBUG, "IDE1 \t");
|
||||
}
|
||||
if (conf->ide0_enable) {
|
||||
/* Enable primary ide interface */
|
||||
word |= (1<<1);
|
||||
/* Enable primary IDE interface. */
|
||||
word |= (1 << 1);
|
||||
printk(BIOS_DEBUG, "IDE0\n");
|
||||
}
|
||||
|
||||
word |= (1<<12);
|
||||
word |= (1<<14);
|
||||
word |= (1 << 12);
|
||||
word |= (1 << 14);
|
||||
|
||||
pci_write_config16(dev, 0x50, word);
|
||||
|
||||
|
||||
byte = 0x20 ; // Latency: 64-->32
|
||||
byte = 0x20; /* Latency: 64-->32 */
|
||||
pci_write_config8(dev, 0xd, byte);
|
||||
|
||||
dword = pci_read_config32(dev, 0xf8);
|
||||
|
|
@ -66,17 +64,16 @@ static void ide_init(struct device *dev)
|
|||
#if CONFIG_PCI_ROM_RUN == 1
|
||||
pci_dev_init(dev);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
static struct device_operations ide_ops = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = ide_init,
|
||||
.scan_bus = 0,
|
||||
// .enable = mcp55_enable,
|
||||
.ops_pci = &mcp55_pci_ops,
|
||||
static struct device_operations ide_ops = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = ide_init,
|
||||
.scan_bus = 0,
|
||||
// .enable = mcp55_enable,
|
||||
.ops_pci = &mcp55_pci_ops,
|
||||
};
|
||||
|
||||
static const struct pci_driver ide_driver __pci_driver = {
|
||||
|
|
@ -84,4 +81,3 @@ static const struct pci_driver ide_driver __pci_driver = {
|
|||
.vendor = PCI_VENDOR_ID_NVIDIA,
|
||||
.device = PCI_DEVICE_ID_NVIDIA_MCP55_IDE,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -54,14 +54,14 @@
|
|||
|
||||
static void lpc_common_init(device_t dev, int master)
|
||||
{
|
||||
uint8_t byte;
|
||||
uint32_t ioapic_base;
|
||||
u8 byte;
|
||||
u32 ioapic_base;
|
||||
|
||||
/* IO APIC initialization */
|
||||
/* IOAPIC initialization. */
|
||||
byte = pci_read_config8(dev, 0x74);
|
||||
byte |= (1<<0); // enable APIC
|
||||
byte |= (1 << 0); /* Enable IOAPIC. */
|
||||
pci_write_config8(dev, 0x74, byte);
|
||||
ioapic_base = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14
|
||||
ioapic_base = pci_read_config32(dev, PCI_BASE_ADDRESS_1); /* 0x14 */
|
||||
|
||||
if (master)
|
||||
setup_ioapic(ioapic_base, 0);
|
||||
|
|
@ -78,24 +78,22 @@ static void enable_hpet(struct device *dev)
|
|||
{
|
||||
unsigned long hpet_address;
|
||||
|
||||
pci_write_config32(dev,0x44, 0xfed00001);
|
||||
hpet_address=pci_read_config32(dev,0x44)& 0xfffffffe;
|
||||
pci_write_config32(dev, 0x44, 0xfed00001);
|
||||
hpet_address=pci_read_config32(dev, 0x44) & 0xfffffffe;
|
||||
printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address);
|
||||
}
|
||||
|
||||
static void lpc_init(device_t dev)
|
||||
{
|
||||
uint8_t byte;
|
||||
uint8_t byte_old;
|
||||
int on;
|
||||
int nmi_option;
|
||||
u8 byte, byte_old;
|
||||
int on, nmi_option;
|
||||
|
||||
lpc_common_init(dev, 1);
|
||||
|
||||
#if 0
|
||||
/* posted memory write enable */
|
||||
/* Posted memory write enable. */
|
||||
byte = pci_read_config8(dev, 0x46);
|
||||
pci_write_config8(dev, 0x46, byte | (1<<0));
|
||||
pci_write_config8(dev, 0x46, byte | (1 << 0));
|
||||
#endif
|
||||
/* power after power fail */
|
||||
|
||||
|
|
@ -104,63 +102,58 @@ static void lpc_init(device_t dev)
|
|||
get_option(&on, "power_on_after_fail");
|
||||
byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
|
||||
byte &= ~0x40;
|
||||
if (!on) {
|
||||
if (!on)
|
||||
byte |= 0x40;
|
||||
}
|
||||
pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
|
||||
printk(BIOS_INFO, "set power %s after power fail\n", on?"on":"off");
|
||||
printk(BIOS_INFO, "set power %s after power fail\n", on ? "on" : "off");
|
||||
#endif
|
||||
/* Throttle the CPU speed down for testing */
|
||||
/* Throttle the CPU speed down for testing. */
|
||||
on = SLOW_CPU_OFF;
|
||||
get_option(&on, "slow_cpu");
|
||||
if(on) {
|
||||
uint16_t pm10_bar;
|
||||
uint32_t dword;
|
||||
pm10_bar = (pci_read_config16(dev, 0x60)&0xff00);
|
||||
outl(((on<<1)+0x10) ,(pm10_bar + 0x10));
|
||||
if (on) {
|
||||
u16 pm10_bar;
|
||||
u32 dword;
|
||||
pm10_bar = (pci_read_config16(dev, 0x60) & 0xff00);
|
||||
outl(((on << 1) + 0x10), (pm10_bar + 0x10));
|
||||
dword = inl(pm10_bar + 0x10);
|
||||
on = 8-on;
|
||||
on = 8 - on;
|
||||
printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n",
|
||||
(on*12)+(on>>1),(on&1)*5);
|
||||
(on * 12) + (on >> 1), (on & 1) * 5);
|
||||
}
|
||||
|
||||
#if 0
|
||||
// default is enabled
|
||||
/* Enable Port 92 fast reset */
|
||||
/* Enable Port 92 fast reset (default is enabled). */
|
||||
byte = pci_read_config8(dev, 0xe8);
|
||||
byte |= ~(1 << 3);
|
||||
pci_write_config8(dev, 0xe8, byte);
|
||||
#endif
|
||||
|
||||
/* Enable Error reporting */
|
||||
/* Set up sync flood detected */
|
||||
/* Enable error reporting. */
|
||||
/* Set up sync flood detected. */
|
||||
byte = pci_read_config8(dev, 0x47);
|
||||
byte |= (1 << 1);
|
||||
pci_write_config8(dev, 0x47, byte);
|
||||
|
||||
/* Set up NMI on errors */
|
||||
byte = inb(0x70); // RTC70
|
||||
/* Set up NMI on errors. */
|
||||
byte = inb(0x70); /* RTC70 */
|
||||
byte_old = byte;
|
||||
nmi_option = NMI_OFF;
|
||||
get_option(&nmi_option, "nmi");
|
||||
if (nmi_option) {
|
||||
byte &= ~(1 << 7); /* set NMI */
|
||||
} else {
|
||||
byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW
|
||||
}
|
||||
if( byte != byte_old) {
|
||||
if (nmi_option)
|
||||
byte &= ~(1 << 7); /* Set NMI. */
|
||||
else
|
||||
byte |= ( 1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW. */
|
||||
if (byte != byte_old)
|
||||
outb(byte, 0x70);
|
||||
}
|
||||
|
||||
/* Initialize the real time clock */
|
||||
/* Initialize the real time clock. */
|
||||
rtc_init(0);
|
||||
|
||||
/* Initialize isa dma */
|
||||
/* Initialize ISA DMA. */
|
||||
isa_dma_init();
|
||||
|
||||
/* Initialize the High Precision Event Timers */
|
||||
/* Initialize the High Precision Event Timers (HPET). */
|
||||
enable_hpet(dev);
|
||||
|
||||
}
|
||||
|
||||
static void mcp55_lpc_read_resources(device_t dev)
|
||||
|
|
@ -191,16 +184,14 @@ static void mcp55_lpc_read_resources(device_t dev)
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief Enable resources for children devices
|
||||
*
|
||||
* @param dev the device whos children's resources are to be enabled
|
||||
* Enable resources for children devices.
|
||||
*
|
||||
* @param dev The device whose children's resources are to be enabled.
|
||||
*/
|
||||
static void mcp55_lpc_enable_childrens_resources(device_t dev)
|
||||
{
|
||||
uint32_t reg, reg_var[4];
|
||||
int i;
|
||||
int var_num = 0;
|
||||
u32 reg, reg_var[4];
|
||||
int i, var_num = 0;
|
||||
struct bus *link;
|
||||
|
||||
reg = pci_read_config32(dev, 0xa0);
|
||||
|
|
@ -208,43 +199,50 @@ static void mcp55_lpc_enable_childrens_resources(device_t dev)
|
|||
for (link = dev->link_list; link; link = link->next) {
|
||||
device_t child;
|
||||
for (child = link->children; child; child = child->sibling) {
|
||||
if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
|
||||
if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
|
||||
struct resource *res;
|
||||
for(res = child->resource_list; res; res = res->next) {
|
||||
unsigned long base, end; // don't need long long
|
||||
if(!(res->flags & IORESOURCE_IO)) continue;
|
||||
for (res = child->resource_list; res; res = res->next) {
|
||||
unsigned long base, end; /* Don't need long long. */
|
||||
if (!(res->flags & IORESOURCE_IO))
|
||||
continue;
|
||||
base = res->base;
|
||||
end = resource_end(res);
|
||||
printk(BIOS_DEBUG, "mcp55 lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end);
|
||||
switch(base) {
|
||||
case 0x3f8: // COM1
|
||||
reg |= (1<<0); break;
|
||||
case 0x2f8: // COM2
|
||||
reg |= (1<<1); break;
|
||||
case 0x378: // Parallal 1
|
||||
reg |= (1<<24); break;
|
||||
case 0x3f0: // FD0
|
||||
reg |= (1<<20); break;
|
||||
case 0x220: // Aduio 0
|
||||
reg |= (1<<8); break;
|
||||
case 0x300: // Midi 0
|
||||
reg |= (1<<12); break;
|
||||
case 0x3f8: /* COM1 */
|
||||
reg |= (1 << 0);
|
||||
break;
|
||||
case 0x2f8: /* COM2 */
|
||||
reg |= (1 << 1);
|
||||
break;
|
||||
case 0x378: /* Parallel 1 */
|
||||
reg |= (1 << 24);
|
||||
break;
|
||||
case 0x3f0: /* FD0 */
|
||||
reg |= (1 << 20);
|
||||
break;
|
||||
case 0x220: /* Audio 0 */
|
||||
reg |= (1 << 8);
|
||||
break;
|
||||
case 0x300: /* Midi 0 */
|
||||
reg |= (1 << 12);
|
||||
break;
|
||||
}
|
||||
if( (base == 0x290) || (base >= 0x400)) {
|
||||
if(var_num>=4) continue; // only 4 var ; compact them ?
|
||||
reg |= (1<<(28+var_num));
|
||||
reg_var[var_num++] = (base & 0xffff)|((end & 0xffff)<<16);
|
||||
if ((base == 0x290)
|
||||
|| (base >= 0x400)) {
|
||||
/* Only 4 var; compact them? */
|
||||
if (var_num >= 4)
|
||||
continue;
|
||||
reg |= (1 << (28 + var_num));
|
||||
reg_var[var_num++] = (base & 0xffff) | ((end & 0xffff) << 16);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
pci_write_config32(dev, 0xa0, reg);
|
||||
for(i=0;i<var_num;i++) {
|
||||
pci_write_config32(dev, 0xa8 + i*4, reg_var[i]);
|
||||
}
|
||||
|
||||
|
||||
for (i = 0; i < var_num; i++)
|
||||
pci_write_config32(dev, 0xa8 + i * 4, reg_var[i]);
|
||||
}
|
||||
|
||||
static void mcp55_lpc_enable_resources(device_t dev)
|
||||
|
|
@ -253,14 +251,14 @@ static void mcp55_lpc_enable_resources(device_t dev)
|
|||
mcp55_lpc_enable_childrens_resources(dev);
|
||||
}
|
||||
|
||||
static struct device_operations lpc_ops = {
|
||||
.read_resources = mcp55_lpc_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = mcp55_lpc_enable_resources,
|
||||
.init = lpc_init,
|
||||
.scan_bus = scan_static_bus,
|
||||
// .enable = mcp55_enable,
|
||||
.ops_pci = &mcp55_pci_ops,
|
||||
static struct device_operations lpc_ops = {
|
||||
.read_resources = mcp55_lpc_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = mcp55_lpc_enable_resources,
|
||||
.init = lpc_init,
|
||||
.scan_bus = scan_static_bus,
|
||||
// .enable = mcp55_enable,
|
||||
.ops_pci = &mcp55_pci_ops,
|
||||
};
|
||||
static const struct pci_driver lpc_driver __pci_driver = {
|
||||
.ops = &lpc_ops,
|
||||
|
|
@ -279,34 +277,38 @@ static const struct pci_driver lpc_driver_lpc2 __pci_driver = {
|
|||
.vendor = PCI_VENDOR_ID_NVIDIA,
|
||||
.device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_2,
|
||||
};
|
||||
|
||||
static const struct pci_driver lpc_driver_lpc3 __pci_driver = {
|
||||
.ops = &lpc_ops,
|
||||
.vendor = PCI_VENDOR_ID_NVIDIA,
|
||||
.device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_3,
|
||||
};
|
||||
|
||||
static const struct pci_driver lpc_driver_lpc4 __pci_driver = {
|
||||
.ops = &lpc_ops,
|
||||
.vendor = PCI_VENDOR_ID_NVIDIA,
|
||||
.device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_4,
|
||||
};
|
||||
|
||||
static const struct pci_driver lpc_driver_lpc5 __pci_driver = {
|
||||
.ops = &lpc_ops,
|
||||
.vendor = PCI_VENDOR_ID_NVIDIA,
|
||||
.device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_5,
|
||||
};
|
||||
|
||||
static const struct pci_driver lpc_driver_lpc6 __pci_driver = {
|
||||
.ops = &lpc_ops,
|
||||
.vendor = PCI_VENDOR_ID_NVIDIA,
|
||||
.device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_6,
|
||||
};
|
||||
|
||||
static struct device_operations lpc_slave_ops = {
|
||||
.read_resources = mcp55_lpc_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = lpc_slave_init,
|
||||
// .enable = mcp55_enable,
|
||||
.ops_pci = &mcp55_pci_ops,
|
||||
static struct device_operations lpc_slave_ops = {
|
||||
.read_resources = mcp55_lpc_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = lpc_slave_init,
|
||||
// .enable = mcp55_enable,
|
||||
.ops_pci = &mcp55_pci_ops,
|
||||
};
|
||||
|
||||
static const struct pci_driver lpc_driver_slave __pci_driver = {
|
||||
|
|
|
|||
|
|
@ -22,37 +22,37 @@
|
|||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
|
||||
#include <arch/io.h>
|
||||
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include "mcp55.h"
|
||||
|
||||
static uint32_t final_reg;
|
||||
static u32 final_reg;
|
||||
|
||||
static device_t find_lpc_dev( device_t dev, unsigned devfn)
|
||||
static device_t find_lpc_dev(device_t dev, unsigned devfn)
|
||||
{
|
||||
|
||||
device_t lpc_dev;
|
||||
|
||||
lpc_dev = dev_find_slot(dev->bus->secondary, devfn);
|
||||
|
||||
if ( !lpc_dev ) return lpc_dev;
|
||||
if (!lpc_dev)
|
||||
return lpc_dev;
|
||||
|
||||
if ((lpc_dev->vendor != PCI_VENDOR_ID_NVIDIA) || (
|
||||
(lpc_dev->device < PCI_DEVICE_ID_NVIDIA_MCP55_LPC) ||
|
||||
(lpc_dev->device > PCI_DEVICE_ID_NVIDIA_MCP55_PRO)
|
||||
) ) {
|
||||
uint32_t id;
|
||||
id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
|
||||
if ( (id < (PCI_VENDOR_ID_NVIDIA | (PCI_DEVICE_ID_NVIDIA_MCP55_LPC << 16))) ||
|
||||
(id > (PCI_VENDOR_ID_NVIDIA | (PCI_DEVICE_ID_NVIDIA_MCP55_PRO << 16)))
|
||||
) {
|
||||
lpc_dev = 0;
|
||||
}
|
||||
(lpc_dev->device > PCI_DEVICE_ID_NVIDIA_MCP55_PRO)))
|
||||
{
|
||||
u32 id;
|
||||
id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
|
||||
if ((id < (PCI_VENDOR_ID_NVIDIA
|
||||
| (PCI_DEVICE_ID_NVIDIA_MCP55_LPC << 16))) ||
|
||||
(id > (PCI_VENDOR_ID_NVIDIA
|
||||
| (PCI_DEVICE_ID_NVIDIA_MCP55_PRO << 16))))
|
||||
{
|
||||
lpc_dev = 0;
|
||||
}
|
||||
}
|
||||
|
||||
return lpc_dev;
|
||||
|
|
@ -60,24 +60,18 @@ static device_t find_lpc_dev( device_t dev, unsigned devfn)
|
|||
|
||||
void mcp55_enable(device_t dev)
|
||||
{
|
||||
device_t lpc_dev = 0;
|
||||
device_t sm_dev = 0;
|
||||
unsigned index = 0;
|
||||
unsigned index2 = 0;
|
||||
uint32_t reg_old, reg;
|
||||
uint8_t byte;
|
||||
unsigned deviceid;
|
||||
unsigned vendorid;
|
||||
|
||||
device_t lpc_dev = 0, sm_dev = 0;
|
||||
unsigned index = 0, index2 = 0;
|
||||
u32 reg_old, reg;
|
||||
u8 byte;
|
||||
unsigned deviceid, vendorid, devfn;
|
||||
struct southbridge_nvidia_mcp55_config *conf;
|
||||
conf = dev->chip_info;
|
||||
int i;
|
||||
|
||||
unsigned devfn;
|
||||
|
||||
if(dev->device==0x0000) {
|
||||
if (dev->device == 0x0000) {
|
||||
vendorid = pci_read_config32(dev, PCI_VENDOR_ID);
|
||||
deviceid = (vendorid>>16) & 0xffff;
|
||||
deviceid = (vendorid >> 16) & 0xffff;
|
||||
// vendorid &= 0xffff;
|
||||
} else {
|
||||
// vendorid = dev->vendor;
|
||||
|
|
@ -85,138 +79,135 @@ void mcp55_enable(device_t dev)
|
|||
}
|
||||
|
||||
devfn = (dev->path.pci.devfn) & ~7;
|
||||
switch(deviceid) {
|
||||
case PCI_DEVICE_ID_NVIDIA_MCP55_HT:
|
||||
return;
|
||||
|
||||
case PCI_DEVICE_ID_NVIDIA_MCP55_SM2://?
|
||||
index = 16;
|
||||
switch (deviceid) {
|
||||
case PCI_DEVICE_ID_NVIDIA_MCP55_HT:
|
||||
return;
|
||||
case PCI_DEVICE_ID_NVIDIA_MCP55_SM2: //?
|
||||
index = 16;
|
||||
break;
|
||||
case PCI_DEVICE_ID_NVIDIA_MCP55_USB:
|
||||
devfn -= (1 << 3);
|
||||
index = 8;
|
||||
break;
|
||||
case PCI_DEVICE_ID_NVIDIA_MCP55_USB2:
|
||||
devfn -= (1 << 3);
|
||||
index = 20;
|
||||
break;
|
||||
case PCI_DEVICE_ID_NVIDIA_MCP55_NIC: // two
|
||||
case PCI_DEVICE_ID_NVIDIA_MCP55_NIC_BRIDGE: // two
|
||||
devfn -= (7 << 3);
|
||||
index = 10;
|
||||
for (i = 0; i < 2; i++) {
|
||||
lpc_dev = find_lpc_dev(dev, devfn - (i << 3));
|
||||
if (!lpc_dev)
|
||||
continue;
|
||||
index -= i;
|
||||
devfn -= (i << 3);
|
||||
break;
|
||||
case PCI_DEVICE_ID_NVIDIA_MCP55_USB:
|
||||
devfn -= (1<<3);
|
||||
index = 8;
|
||||
}
|
||||
break;
|
||||
case PCI_DEVICE_ID_NVIDIA_MCP55_AZA:
|
||||
devfn -= (5 << 3);
|
||||
index = 11;
|
||||
break;
|
||||
case PCI_DEVICE_ID_NVIDIA_MCP55_IDE:
|
||||
devfn -= (3 << 3);
|
||||
index = 14;
|
||||
break;
|
||||
case PCI_DEVICE_ID_NVIDIA_MCP55_SATA0: // three
|
||||
case PCI_DEVICE_ID_NVIDIA_MCP55_SATA1: // three
|
||||
devfn -= (4 << 3);
|
||||
index = 22;
|
||||
i = (dev->path.pci.devfn) & 7;
|
||||
if (i > 0)
|
||||
index -= (i + 3);
|
||||
break;
|
||||
case PCI_DEVICE_ID_NVIDIA_MCP55_PCI:
|
||||
devfn -= (5 << 3);
|
||||
index = 15;
|
||||
break;
|
||||
case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_A:
|
||||
devfn -= (0x9 << 3); // to LPC
|
||||
index2 = 9;
|
||||
break;
|
||||
case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_B_C: // two
|
||||
devfn -= (0xa << 3); // to LPC
|
||||
index2 = 8;
|
||||
for (i = 0; i < 2; i++) {
|
||||
lpc_dev = find_lpc_dev(dev, devfn - (i << 3));
|
||||
if (!lpc_dev)
|
||||
continue;
|
||||
index2 -= i;
|
||||
devfn -= (i << 3);
|
||||
break;
|
||||
case PCI_DEVICE_ID_NVIDIA_MCP55_USB2:
|
||||
devfn -= (1<<3);
|
||||
index = 20;
|
||||
break;
|
||||
case PCI_DEVICE_ID_NVIDIA_MCP55_NIC: //two
|
||||
case PCI_DEVICE_ID_NVIDIA_MCP55_NIC_BRIDGE://two
|
||||
devfn -= (7<<3);
|
||||
index = 10;
|
||||
for(i=0;i<2;i++) {
|
||||
lpc_dev = find_lpc_dev(dev, devfn - (i<<3));
|
||||
if(!lpc_dev) continue;
|
||||
index -= i;
|
||||
devfn -= (i<<3);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case PCI_DEVICE_ID_NVIDIA_MCP55_AZA:
|
||||
devfn -= (5<<3);
|
||||
index = 11;
|
||||
break;
|
||||
case PCI_DEVICE_ID_NVIDIA_MCP55_IDE:
|
||||
devfn -= (3<<3);
|
||||
index = 14;
|
||||
break;
|
||||
case PCI_DEVICE_ID_NVIDIA_MCP55_SATA0: //three
|
||||
case PCI_DEVICE_ID_NVIDIA_MCP55_SATA1: //three
|
||||
devfn -= (4<<3);
|
||||
index = 22;
|
||||
i = (dev->path.pci.devfn) & 7;
|
||||
if(i>0) {
|
||||
index -= (i+3);
|
||||
}
|
||||
break;
|
||||
case PCI_DEVICE_ID_NVIDIA_MCP55_PCI:
|
||||
devfn -= (5<<3);
|
||||
index = 15;
|
||||
break;
|
||||
case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_A:
|
||||
devfn -= (0x9<<3); // to LPC
|
||||
index2 = 9;
|
||||
break;
|
||||
case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_B_C: //two
|
||||
devfn -= (0xa<<3); // to LPC
|
||||
index2 = 8;
|
||||
for(i=0;i<2;i++) {
|
||||
lpc_dev = find_lpc_dev(dev, devfn - (i<<3));
|
||||
if(!lpc_dev) continue;
|
||||
index2 -= i;
|
||||
devfn -= (i<<3);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_D:
|
||||
devfn -= (0xc<<3); // to LPC
|
||||
index2 = 6;
|
||||
break;
|
||||
case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_E:
|
||||
devfn -= (0xd<<3); // to LPC
|
||||
index2 = 5;
|
||||
break;
|
||||
case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_F:
|
||||
devfn -= (0xe<<3); // to LPC
|
||||
index2 = 4;
|
||||
break;
|
||||
default:
|
||||
index = 0;
|
||||
}
|
||||
break;
|
||||
case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_D:
|
||||
devfn -= (0xc << 3); // to LPC
|
||||
index2 = 6;
|
||||
break;
|
||||
case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_E:
|
||||
devfn -= (0xd << 3); // to LPC
|
||||
index2 = 5;
|
||||
break;
|
||||
case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_F:
|
||||
devfn -= (0xe << 3); // to LPC
|
||||
index2 = 4;
|
||||
break;
|
||||
default:
|
||||
index = 0;
|
||||
}
|
||||
|
||||
if(!lpc_dev)
|
||||
if (!lpc_dev)
|
||||
lpc_dev = find_lpc_dev(dev, devfn);
|
||||
|
||||
if ( !lpc_dev ) return;
|
||||
if (!lpc_dev)
|
||||
return;
|
||||
|
||||
if(index2!=0) {
|
||||
if (index2 != 0) {
|
||||
sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1);
|
||||
if(!sm_dev) return;
|
||||
|
||||
if ( sm_dev ) {
|
||||
reg_old = reg = pci_read_config32(sm_dev, 0xe4);
|
||||
|
||||
if (!dev->enabled) { //disable it
|
||||
reg |= (1<<index2);
|
||||
}
|
||||
|
||||
if (reg != reg_old) {
|
||||
if (!sm_dev)
|
||||
return;
|
||||
if (sm_dev) {
|
||||
reg_old = reg = pci_read_config32(sm_dev, 0xe4);
|
||||
if (!dev->enabled)
|
||||
reg |= (1<<index2); /* Disable it. */
|
||||
if (reg != reg_old)
|
||||
pci_write_config32(sm_dev, 0xe4, reg);
|
||||
}
|
||||
}
|
||||
|
||||
index2 = 0;
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
if ( index == 0) { // for LPC
|
||||
|
||||
// expose ioapic base
|
||||
if (index == 0) { // for LPC
|
||||
/* Expose IOAPIC base. */
|
||||
byte = pci_read_config8(lpc_dev, 0x74);
|
||||
byte |= ((1<<1)); // expose the BAR
|
||||
byte |= (1 << 1); /* Expose the BAR. */
|
||||
pci_write_config8(dev, 0x74, byte);
|
||||
|
||||
// expose trap base
|
||||
/* Expose trap base. */
|
||||
byte = pci_read_config8(lpc_dev, 0xdd);
|
||||
byte |= ((1<<0)|(1<<3)); // expose the BAR and enable write
|
||||
byte |= (1 << 0) | (1 << 3); /* Expose BAR and enable write. */
|
||||
pci_write_config8(dev, 0xdd, byte);
|
||||
|
||||
return;
|
||||
|
||||
}
|
||||
|
||||
if( index == 16) {
|
||||
if (index == 16) {
|
||||
sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1);
|
||||
if(!sm_dev) return;
|
||||
if (!sm_dev)
|
||||
return;
|
||||
|
||||
final_reg = pci_read_config32(sm_dev, 0xe8);
|
||||
final_reg &= ~((1<<16)|(1<<8)|(1<<20)|(1<<14)|(1<<22)|(1<<18)|(1<<17)|(1<<15)|(1<<11)|(1<<10)|(1<<9));
|
||||
pci_write_config32(sm_dev, 0xe8, final_reg); //enable all at first
|
||||
final_reg &= ~((1 << 16) | (1 << 8) | (1 << 20) | (1 << 14)
|
||||
| (1 << 22) | (1 << 18) | (1 << 17) | (1 << 15)
|
||||
| (1 << 11) | (1 << 10) | (1 << 9));
|
||||
pci_write_config32(sm_dev, 0xe8, final_reg); /* Enable all at first. */
|
||||
|
||||
#if 0
|
||||
reg_old = reg = pci_read_config32(sm_dev, 0xe4);
|
||||
// reg |= (1<<0);
|
||||
reg &= ~(0x3f<<4);
|
||||
// reg |= (1 << 0);
|
||||
reg &= ~(0x3f << 4);
|
||||
if (reg != reg_old) {
|
||||
printk(BIOS_DEBUG, "mcp55.c pcie enabled\n");
|
||||
pci_write_config32(sm_dev, 0xe4, reg);
|
||||
|
|
@ -225,21 +216,22 @@ void mcp55_enable(device_t dev)
|
|||
}
|
||||
|
||||
if (!dev->enabled) {
|
||||
final_reg |= (1 << index);// disable it
|
||||
//The reason for using final_reg, if diable func 1, the func 2 will be func 1 so We need disable them one time.
|
||||
final_reg |= (1 << index); /* Disable it. */
|
||||
/*
|
||||
* The reason for using final_reg, if diable func 1,
|
||||
* the func 2 will be func 1, so we need disable them one time.
|
||||
*/
|
||||
}
|
||||
|
||||
if(index == 9 ) { //NIC1 is the final, We need update final reg to 0xe8
|
||||
/* NIC1 is the final, we need update final reg to 0xe8. */
|
||||
if (index == 9) {
|
||||
sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1);
|
||||
if(!sm_dev) return;
|
||||
if (!sm_dev)
|
||||
return;
|
||||
reg_old = pci_read_config32(sm_dev, 0xe8);
|
||||
if (final_reg != reg_old) {
|
||||
if (final_reg != reg_old)
|
||||
pci_write_config32(sm_dev, 0xe8, final_reg);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
static void mcp55_set_subsystem(device_t dev, unsigned vendor, unsigned device)
|
||||
|
|
@ -250,9 +242,9 @@ static void mcp55_set_subsystem(device_t dev, unsigned vendor, unsigned device)
|
|||
|
||||
struct pci_operations mcp55_pci_ops = {
|
||||
.set_subsystem = mcp55_set_subsystem,
|
||||
};
|
||||
};
|
||||
|
||||
struct chip_operations southbridge_nvidia_mcp55_ops = {
|
||||
CHIP_NAME("NVIDIA MCP55 Southbridge")
|
||||
.enable_dev = mcp55_enable,
|
||||
.enable_dev = mcp55_enable,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -19,13 +19,13 @@
|
|||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef MCP55_H
|
||||
#define MCP55_H
|
||||
#ifndef SOUTHBRIDGE_NVIDIA_MCP55_MCP55_H
|
||||
#define SOUTHBRIDGE_NVIDIA_MCP55_MCP55_H
|
||||
|
||||
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
|
||||
#define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
|
||||
#define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
|
||||
#else
|
||||
#define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
|
||||
#define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
|
||||
#endif
|
||||
|
||||
#ifndef __PRE_RAM__
|
||||
|
|
@ -39,4 +39,4 @@ void mcp55_enable_usbdebug(unsigned int port);
|
|||
#endif
|
||||
#endif
|
||||
|
||||
#endif /* MCP55_H */
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -35,91 +35,97 @@ static int phy_read(u32 base, unsigned phy_addr, unsigned phy_reg)
|
|||
{
|
||||
u32 dword;
|
||||
unsigned loop = 0x100;
|
||||
write32(base+0x190, 0x8000); //Clear MDIO lock bit
|
||||
mdelay(1);
|
||||
dword = read32(base+0x190);
|
||||
if(dword & (1<<15)) return -1;
|
||||
|
||||
write32(base+0x180, 1);
|
||||
write32(base + 0x190, (phy_addr<<5) | (phy_reg));
|
||||
do{
|
||||
write32(base + 0x190, 0x8000); /* Clear MDIO lock bit. */
|
||||
mdelay(1);
|
||||
dword = read32(base + 0x190);
|
||||
if (dword & (1 << 15))
|
||||
return -1;
|
||||
|
||||
write32(base + 0x180, 1);
|
||||
write32(base + 0x190, (phy_addr << 5) | (phy_reg));
|
||||
do {
|
||||
dword = read32(base + 0x190);
|
||||
if(--loop==0) return -4;
|
||||
} while ((dword & (1<<15)) );
|
||||
if (--loop==0)
|
||||
return -4;
|
||||
} while ((dword & (1 << 15)));
|
||||
|
||||
dword = read32(base + 0x180);
|
||||
if(dword & 1) return -3;
|
||||
if (dword & 1)
|
||||
return -3;
|
||||
|
||||
dword = read32(base + 0x194);
|
||||
|
||||
return dword;
|
||||
|
||||
}
|
||||
|
||||
static void phy_detect(u32 base)
|
||||
{
|
||||
u32 dword;
|
||||
int i;
|
||||
int val;
|
||||
int i, val;
|
||||
unsigned id;
|
||||
dword = read32(base+0x188);
|
||||
dword &= ~(1<<20);
|
||||
write32(base+0x188, dword);
|
||||
|
||||
dword = read32(base + 0x188);
|
||||
dword &= ~(1 << 20);
|
||||
write32(base + 0x188, dword);
|
||||
|
||||
phy_read(base, 0, 1);
|
||||
|
||||
for(i=1; i<=32; i++) {
|
||||
for (i = 1; i <= 32; i++) {
|
||||
int phyaddr = i & 0x1f;
|
||||
val = phy_read(base, phyaddr, 1);
|
||||
if(val<0) continue;
|
||||
if((val & 0xffff) == 0xfffff) continue;
|
||||
if((val & 0xffff) == 0) continue;
|
||||
if(!(val & 1)) {
|
||||
break; // Ethernet PHY
|
||||
}
|
||||
if (val < 0)
|
||||
continue;
|
||||
if ((val & 0xffff) == 0xfffff)
|
||||
continue;
|
||||
if ((val & 0xffff) == 0)
|
||||
continue;
|
||||
if (!(val & 1))
|
||||
break; /* Ethernet PHY */
|
||||
|
||||
val = phy_read(base, phyaddr, 3);
|
||||
if (val < 0 || val == 0xffff) continue;
|
||||
if (val < 0 || val == 0xffff)
|
||||
continue;
|
||||
id = val & 0xfc00;
|
||||
val = phy_read(base, phyaddr, 2);
|
||||
if (val < 0 || val == 0xffff) continue;
|
||||
id |= ((val & 0xffff)<<16);
|
||||
printk(BIOS_DEBUG, "MCP55 MAC PHY ID 0x%08x PHY ADDR %d\n", id, i);
|
||||
// if((id == 0xe0180000) || (id==0x0032cc00))
|
||||
if (val < 0 || val == 0xffff)
|
||||
continue;
|
||||
id |= ((val & 0xffff) << 16);
|
||||
printk(BIOS_DEBUG, "MCP55 MAC PHY ID 0x%08x PHY ADDR %d\n",
|
||||
id, i);
|
||||
// if ((id == 0xe0180000) || (id == 0x0032cc00))
|
||||
break;
|
||||
}
|
||||
|
||||
if(i>32) {
|
||||
if (i > 32)
|
||||
printk(BIOS_DEBUG, "MCP55 MAC PHY not found\n");
|
||||
}
|
||||
}
|
||||
|
||||
static void nic_init(struct device *dev)
|
||||
{
|
||||
u32 mac_h, mac_l;
|
||||
u32 mac_h, mac_l, base;
|
||||
int eeprom_valid = 0;
|
||||
struct southbridge_nvidia_mcp55_config *conf;
|
||||
|
||||
static u32 nic_index = 0;
|
||||
|
||||
u32 base;
|
||||
struct resource *res;
|
||||
|
||||
res = find_resource(dev, 0x10);
|
||||
|
||||
if(!res) return;
|
||||
if (!res)
|
||||
return;
|
||||
|
||||
base = res->base;
|
||||
|
||||
phy_detect(base);
|
||||
|
||||
#define NvRegPhyInterface 0xC0
|
||||
#define PHY_RGMII 0x10000000
|
||||
#define PHY_RGMII 0x10000000
|
||||
|
||||
write32(base + NvRegPhyInterface, PHY_RGMII);
|
||||
|
||||
conf = dev->chip_info;
|
||||
|
||||
if(conf->mac_eeprom_smbus != 0) {
|
||||
if (conf->mac_eeprom_smbus != 0) {
|
||||
// read MAC address from EEPROM at first
|
||||
struct device *dev_eeprom;
|
||||
dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus, conf->mac_eeprom_addr);
|
||||
|
|
|
|||
|
|
@ -31,9 +31,8 @@
|
|||
|
||||
static void pci_init(struct device *dev)
|
||||
{
|
||||
|
||||
uint32_t dword;
|
||||
uint16_t word;
|
||||
u32 dword;
|
||||
u16 word;
|
||||
device_t pci_domain_dev;
|
||||
struct resource *mem, *pref;
|
||||
|
||||
|
|
|
|||
|
|
@ -30,9 +30,8 @@
|
|||
|
||||
static void pcie_init(struct device *dev)
|
||||
{
|
||||
|
||||
/* Enable pci error detecting */
|
||||
uint32_t dword;
|
||||
u32 dword;
|
||||
|
||||
/* System error enable */
|
||||
dword = pci_read_config32(dev, 0x04);
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@
|
|||
|
||||
static void sata_init(struct device *dev)
|
||||
{
|
||||
uint32_t dword;
|
||||
u32 dword;
|
||||
|
||||
struct southbridge_nvidia_mcp55_config *conf;
|
||||
conf = dev->chip_info;
|
||||
|
|
|
|||
|
|
@ -46,7 +46,7 @@ static int lsmbus_recv_byte(device_t dev)
|
|||
return do_smbus_recv_byte(res->base, device);
|
||||
}
|
||||
|
||||
static int lsmbus_send_byte(device_t dev, uint8_t val)
|
||||
static int lsmbus_send_byte(device_t dev, u8 val)
|
||||
{
|
||||
unsigned device;
|
||||
struct resource *res;
|
||||
|
|
@ -60,7 +60,7 @@ static int lsmbus_send_byte(device_t dev, uint8_t val)
|
|||
return do_smbus_send_byte(res->base, device, val);
|
||||
}
|
||||
|
||||
static int lsmbus_read_byte(device_t dev, uint8_t address)
|
||||
static int lsmbus_read_byte(device_t dev, u8 address)
|
||||
{
|
||||
unsigned device;
|
||||
struct resource *res;
|
||||
|
|
@ -74,7 +74,7 @@ static int lsmbus_read_byte(device_t dev, uint8_t address)
|
|||
return do_smbus_read_byte(res->base, device, address);
|
||||
}
|
||||
|
||||
static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val)
|
||||
static int lsmbus_write_byte(device_t dev, u8 address, u8 val)
|
||||
{
|
||||
unsigned device;
|
||||
struct resource *res;
|
||||
|
|
|
|||
|
|
@ -33,7 +33,7 @@ extern struct ehci_debug_info dbg_info;
|
|||
|
||||
static void usb2_init(struct device *dev)
|
||||
{
|
||||
uint32_t dword;
|
||||
u32 dword;
|
||||
dword = pci_read_config32(dev, 0xf8);
|
||||
dword |= 40;
|
||||
pci_write_config32(dev, 0xf8, dword);
|
||||
|
|
|
|||
Loading…
Reference in New Issue