haswell: Add magic to turn on grahpics in normal mode
The haswell i915 kernel driver apparently expects the VBIOS to set a few specific registers. This sequence is enough to make the driver happy without executing the VBIOS. This also makes graphics work after suspend/resume. Change-Id: I34937d55ffff8a9445442e6e6ca1bfc49869da63 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56806 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4195 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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@ -131,17 +131,13 @@ static void gma_pm_init_pre_vbios(struct device *dev)
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gtt_write(0x0a094, 0x00040000);
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}
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static void gma_pm_init_post_vbios(struct device *dev)
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static void gma_setup_panel(struct device *dev)
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{
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struct northbridge_intel_haswell_config *conf = dev->chip_info;
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u32 reg32;
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printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n");
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/* Disable Force Wake */
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gtt_write(0x0a188, 0x00010000);
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gtt_poll(0x130044, 1 << 0, 0 << 0);
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/* Setup Digital Port Hotplug */
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reg32 = gtt_read(0xc4030);
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if (!reg32) {
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@ -187,6 +183,22 @@ static void gma_pm_init_post_vbios(struct device *dev)
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}
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}
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static void gma_pm_init_post_vbios(struct device *dev)
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{
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extern int oprom_is_loaded;
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if (!oprom_is_loaded) {
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/* Magic to force graphics into happy state for kernel */
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gtt_write(0xc7204, 0xabcd000f); /* panel power up */
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gtt_write(0x45400, 0x80000000); /* power well enable */
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gtt_write(0x64000, 0x00000091); /* DDI-A enable */
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}
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/* Disable Force Wake */
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gtt_write(0x0a188, 0x00010000);
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gtt_poll(0x130044, 1 << 0, 0 << 0);
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}
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static void gma_func0_init(struct device *dev)
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{
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int lightup_ok = 0;
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@ -203,9 +215,13 @@ static void gma_func0_init(struct device *dev)
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* So it's almost like having two hardcodes.
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*/
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graphics_base = dev->resource_list[1].base;
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/* Init graphics power management */
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gma_pm_init_pre_vbios(dev);
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/* Post VBIOS init */
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gma_setup_panel(dev);
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#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
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printk(BIOS_SPEW, "NATIVE graphics, run native enable\n");
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u32 iobase, mmiobase, physbase;
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