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Intel cpus: use CPU_ADDR_BITS from Kconfig during CAR 

Default CPU_ADDR_BITS is 36.

For Atom (model_106cx) use 32. This model is known to
fail execution-in-place (XIP) with the default 36.

Pentium M should use 32, but doesn't even with this patch.
Some Xeon and CORE(2) models should use 38 or 40.

Change-Id: If604badcdc578c4f4bc7d30da2f61397ec0d754c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/639
Tested-by: build bot (Jenkins)
Reviewed-by: Sven Schnelle <svens@stackframe.org>
This commit is contained in:
Kyösti Mälkki 2012-06-28 21:26:41 +03:00 committed by Sven Schnelle
parent 89f04a6d68
commit c7fb2ae67b
5 changed files with 13 additions and 8 deletions
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9
src/cpu/intel/model_106cx/Kconfig
View File

@ -3,3 +3,12 @@ config CPU_INTEL_MODEL_106CX
select SMP select SMP
select SSE2 select SSE2
select UDELAY_LAPIC select UDELAY_LAPIC
if CPU_INTEL_MODEL_106CX
config CPU_ADDR_BITS
int
default 32
endif

3
src/cpu/intel/model_106cx/cache_as_ram.inc
View File

@ -23,8 +23,7 @@
#include <cpu/x86/cache.h> #include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h> #include <cpu/x86/post_code.h>
#define CPU_MAXPHYADDR 32 #define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1)
#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1)
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE

3
src/cpu/intel/model_206ax/cache_as_ram.inc
View File

@ -32,8 +32,7 @@
#define CACHE_MRC_BASE (0xFFFFFFFF - CACHE_MRC_BYTES) #define CACHE_MRC_BASE (0xFFFFFFFF - CACHE_MRC_BYTES)
#define CACHE_MRC_MASK (~CACHE_MRC_BYTES) #define CACHE_MRC_MASK (~CACHE_MRC_BYTES)
#define CPU_MAXPHYSADDR 36 #define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1)
#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYSADDR - 32) - 1)
#define NoEvictMod_MSR 0x2e0 #define NoEvictMod_MSR 0x2e0

3
src/cpu/intel/model_6ex/cache_as_ram.inc
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@ -23,8 +23,7 @@
#include <cpu/x86/cache.h> #include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h> #include <cpu/x86/post_code.h>
#define CPU_MAXPHYADDR 36 #define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1)
#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1)
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE

3
src/cpu/intel/model_6fx/cache_as_ram.inc
View File

@ -23,8 +23,7 @@
#include <cpu/x86/cache.h> #include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h> #include <cpu/x86/post_code.h>
#define CPU_MAXPHYADDR 36 #define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1)
#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1)
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE