inteltool: Add support for H65 Express chipset
Added few MCH and DMI registers for H65E. Description of them can be found at "2nd Generation Intel Core Processors Family datasheet" Change-Id: If4fee35bb5a09b04ea0684be9cbd3c1e9084b934 Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-on: http://review.coreboot.org/1258 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
This commit is contained in:
Anton Kochkov
Peter Stuge
parent
8bacc40fc7
commit
c7fc4422a0
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@ -54,6 +54,7 @@ static const struct {
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82G33, "P35/G33/G31/P31" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q33, "Q33" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58, "X58" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM65E, "HM65 Express" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GS45, "GS45ME" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_DXXX, "Atom D400/500 Series" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_NXXX, "Atom N400 Series" },
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@ -102,6 +102,8 @@
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/* 82371AB/EB/MB use the same device ID value. */
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#define PCI_DEVICE_ID_INTEL_82371XX 0x7110
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#define PCI_DEVICE_ID_INTEL_HM65E 0x0104
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#define ARRAY_SIZE(a) ((int)(sizeof(a) / sizeof((a)[0])))
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#if !defined(__DARWIN__) && !defined(__FreeBSD__)
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@ -23,6 +23,47 @@
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#include <inttypes.h>
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#include "inteltool.h"
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static const io_register_t sandybridge_mch_registers[] = {
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/* Channel 0 */
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{ 0x4000, 4, "TC_DBP_C0" }, // Timing of DDR Bin Parameters
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{ 0x4004, 4, "TC_RAP_C0" }, // Timing of DDR Regular Access Parameters
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{ 0x4028, 4, "SC_IO_LATENCY_C0" }, // IO Latency Configuration
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{ 0x42A4, 4, "TC_SRFTP_C0" }, // Self-Refresh Timing Parameters
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{ 0x40B0, 4, "PM_PDWN_config_C0" }, // Power-down Configuration
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{ 0x4294, 4, "TC_RFP_C0" }, // Refresh Parameters
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{ 0x4298, 4, "TC_RFTP_C0" }, // Refresh Timing Parameters
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/* Channel 1 */
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{ 0x4400, 4, "TC_DBP_C1" }, // Timing of DDR Bin Parameters
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{ 0x4404, 4, "TC_RAP_C1" }, // Timing of DDR Regular Access Parameters
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{ 0x4428, 4, "SC_IO_LATENCY_C1" }, // IO Latency Configuration
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{ 0x46A4, 4, "TC_SRFTP_C1" }, // Self-Refresh Timing Parameters
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{ 0x44B0, 4, "PM_PDWN_config_C1" }, // Power-down Configuration
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{ 0x4694, 4, "TC_RFP_C1" }, // Refresh Parameters
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{ 0x4698, 4, "TC_RFTP_C1" }, // Refresh Timing Parameters
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/* Integrated Memory Peripheral Hub (IMPH) */
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{ 0x740C, 4, "CRDTCTL3" }, // Credit Control 3
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/* Common Registers */
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{ 0x5000, 4, "MAD_CHNL" }, // Address decoder Channel Configuration
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{ 0x5004, 4, "MAD_DIMM_ch0" }, // Address Decode Channel 0
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{ 0x5008, 4, "MAD_DIMM_ch1" }, // Address Decode Channel 1
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{ 0x5060, 4, "PM_SREF_config" }, // Self Refresh Configuration
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/* MMIO Registers Broadcast Group */
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{ 0x4CB0, 4, "PM_PDWN_config" }, // Power-down Configuration
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{ 0x4F84, 4, "PM_CMD_PWR" }, // Power Management Command Power
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{ 0x4F88, 4, "PM_BW_LIMIT_config" }, // BW Limit Configuration
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{ 0x4F8C, 4, "RESERVED" }, // Reserved, default value - 0xFF1D1519
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/* PCU MCHBAR Registers */
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{ 0x5880, 4, "MEM_TRML_ESTIMATION_CONFIG" }, // Memory Thermal Estimation Configuration
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{ 0x5884, 4, "RESERVED" }, // Reserved
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{ 0x5888, 4, "MEM_TRML_THRESHOLDS_CONFIG" }, // Memory Thermal Thresholds Configuration
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{ 0x58A0, 4, "MEM_TRML_STATUS_REPORT" }, // Memory Thermal Status Report
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{ 0x58A4, 4, "MEM_TRML_TEMPERATURE_REPORT" }, // Memory Thermal Temperature Report
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{ 0x58A8, 4, "MEM_TRML_INTERRUPT" }, // Memory Thermal Interrupt
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{ 0x5948, 4, "GT_PERF_STATUS" }, // GT Performance Status
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{ 0x5998, 4, "RP_STATE_CAP" }, // RP State Capability
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{ 0x5D10, 8, "SSKPD" }, // Sticky Scratchpad Data
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};
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/*
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* (G)MCH MMIO Config Space
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*/
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@ -31,6 +72,7 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc)
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int i, size = (16 * 1024);
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volatile uint8_t *mchbar;
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uint64_t mchbar_phys;
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const io_register_t *mch_registers = NULL;
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struct pci_dev *nb_device6; /* "overflow device" on i865 */
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uint16_t pcicmd6;
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@ -115,6 +157,11 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc)
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mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe;
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mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
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break;
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case PCI_DEVICE_ID_INTEL_HM65E:
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mchbar_phys = pci_read_long(nb, 0x48) & 0xffff8000;
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mch_registers = sandybridge_mch_registers;
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size = ARRAY_SIZE(sandybridge_mch_registers);
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break;
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default:
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printf("Error: Dumping MCHBAR on this northbridge is not (yet) supported.\n");
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return 1;
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@ -135,10 +182,41 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc)
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else
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printf("MCHBAR = 0x%08" PRIx64 " (MEM)\n\n", mchbar_phys);
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if (mch_registers != NULL) {
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for (i = 0; i < size; i++) {
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switch (mch_registers[i].size) {
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case 8:
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printf("mchbase+0x%04x: 0x%08lx (%s)\n",
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mch_registers[i].addr,
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*(uint64_t *)(mchbar+mch_registers[i].addr),
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mch_registers[i].name);
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break;
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case 4:
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printf("mchbase+0x%04x: 0x%08x (%s)\n",
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mch_registers[i].addr,
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*(uint32_t *)(mchbar+mch_registers[i].addr),
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mch_registers[i].name);
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break;
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case 2:
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printf("mchbase+0x%04x: 0x%04x (%s)\n",
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mch_registers[i].addr,
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*(uint16_t *)(mchbar+mch_registers[i].addr),
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mch_registers[i].name);
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break;
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case 1:
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printf("mchbase+0x%04x: 0x%02x (%s)\n",
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mch_registers[i].addr,
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*(uint8_t *)(mchbar+mch_registers[i].addr),
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mch_registers[i].name);
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break;
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}
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}
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} else {
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for (i = 0; i < size; i += 4) {
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if (*(uint32_t *)(mchbar + i))
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printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(mchbar+i));
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}
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}
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unmap_physical((void *)mchbar, size);
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return 0;
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@ -2,6 +2,7 @@
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* inteltool - dump all registers on an Intel CPU + chipset based system.
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*
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* Copyright (C) 2008-2010 by coresystems GmbH
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* Copyright (C) 2012 Anton Kochkov
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -22,6 +23,58 @@
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#include <inttypes.h>
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#include "inteltool.h"
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static const io_register_t sandybridge_dmi_registers[] = {
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{ 0x00, 4, "DMI VCECH" }, // DMI Virtual Channel Enhanced Capability
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{ 0x04, 4, "DMI PVCCAP1" }, // DMI Port VC Capability Register 1
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{ 0x08, 4, "DMI PVVAP2" }, // DMI Port VC Capability Register 2
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{ 0x0C, 2, "DMI PVCCTL" }, // DMI Port VC Control
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/* { 0x0E, 2, "RSVD" }, // Reserved */
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{ 0x10, 4, "DMI VC0RCAP" }, // DMI VC0 Resource Capability
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{ 0x14, 4, "DMI VC0RCTL" }, // DMI VC0 Resource Control
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/* { 0x18, 2, "RSVD" }, // Reserved */
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{ 0x1A, 2, "DMI VC0RSTS" }, // DMI VC0 Resource Status
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{ 0x1C, 4, "DMI VC1RCAP" }, // DMI VC1 Resource Capability
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{ 0x20, 4, "DMI VC1RCTL" }, // DMI VC1 Resource Control
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/* { 0x24, 2, "RSVD" }, // Reserved */
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{ 0x26, 2, "DMI VC1RSTS" }, // DMI VC1 Resource Status
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{ 0x28, 4, "DMI VCPRCAP" }, // DMI VCp Resource Capability
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{ 0x2C, 4, "DMI VCPRCTL" }, // DMI VCp Resource Control
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/* { 0x30, 2, "RSVD" }, // Reserved */
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{ 0x32, 2, "DMI VCPRSTS" }, // DMI VCp Resource Status
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{ 0x34, 4, "DMI VCMRCAP" }, // DMI VCm Resource Capability
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{ 0x38, 4, "DMI VCMRCTL" }, // DMI VCm Resource Control
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/* { 0x3C, 2, "RSVD" }, // Reserved */
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{ 0x3E, 2, "DMI VCMRSTS" }, // DMI VCm Resource Status
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/* { 0x40, 4, "RSVD" }, // Reserved */
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{ 0x44, 4, "DMI ESC" }, // DMI Element Self Description
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/* { 0x48, 8, "RSVD" }, // Reserved */
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{ 0x50, 4, "DMI LE1D" }, // DMI Link Entry 1 Description
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/* { 0x54, 4, "RSVD" }, // Reserved */
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{ 0x58, 4, "DMI LE1A" }, // DMI Link Entry 1 Address
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{ 0x5C, 4, "DMI LUE1A" }, // DMI Link Upper Entry 1 Address
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{ 0x60, 4, "DMI LE2D" }, // DMI Link Entry 2 Description
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/* { 0x64, 4, "RSVD" }, // Reserved */
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{ 0x68, 4, "DMI LE2A" }, // DMI Link Entry 2 Address
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/* { 0x6C, 4, "RSVD" }, // Reserved
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{ 0x70, 8, "RSVD" }, // Reserved
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{ 0x78, 8, "RSVD" }, // Reserved
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{ 0x80, 4, "RSVD" }, // Reserved */
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{ 0x84, 4, "LCAP" }, // Link Capabilities
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{ 0x88, 2, "LCTL" }, // Link Control
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{ 0x8A, 2, "LSTS" }, // Link Status
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/* { 0x8C, 4, "RSVD" }, // Reserved
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{ 0x90, 4, "RSVD" }, // Reserved
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{ 0x94, 4, "RSVD" }, // Reserved */
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{ 0x98, 2, "LCTL2" }, // Link Control 2
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{ 0x9A, 2, "LSTS2" }, // Link Status 2
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/* ... - Reserved */
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{ 0xBC0, 4, "AFE_BMUF0" }, // AFE BMU Configuration Function 0
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{ 0xBC4, 4, "RSVD" }, // Reserved
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{ 0xBC8, 4, "RSVD" }, // Reserved
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{ 0xBCC, 4, "AFE_BMUT0" }, // AFE BMU Configuration Test 0
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/* ... - Reserved */
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};
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/*
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* Egress Port Root Complex MMIO configuration space
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*/
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@ -91,6 +144,7 @@ int print_dmibar(struct pci_dev *nb)
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int i, size = (4 * 1024);
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volatile uint8_t *dmibar;
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uint64_t dmibar_phys;
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const io_register_t *dmi_registers = NULL;
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printf("\n============= DMIBAR ============\n\n");
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@ -124,6 +178,11 @@ int print_dmibar(struct pci_dev *nb)
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case PCI_DEVICE_ID_INTEL_X58:
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dmibar_phys = pci_read_long(nb, 0x50) & 0xfffff000;
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break;
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case PCI_DEVICE_ID_INTEL_HM65E:
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dmibar_phys = pci_read_long(nb, 0x68) & 0xfffff000;
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dmi_registers = sandybridge_dmi_registers;
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size = ARRAY_SIZE(sandybridge_dmi_registers);
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break;
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default:
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printf("Error: Dumping DMIBAR on this northbridge is not (yet) supported.\n");
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return 1;
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@ -137,10 +196,35 @@ int print_dmibar(struct pci_dev *nb)
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}
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printf("DMIBAR = 0x%08" PRIx64 " (MEM)\n\n", dmibar_phys);
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if (dmi_registers != NULL) {
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for (i = 0; i < size; i++) {
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switch (dmi_registers[i].size) {
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case 4:
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printf("dmibase+0x%04x: 0x%08x (%s)\n",
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dmi_registers[i].addr,
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*(uint32_t *)(dmibar+dmi_registers[i].addr),
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dmi_registers[i].name);
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break;
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case 2:
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printf("dmibase+0x%04x: 0x%04x (%s)\n",
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dmi_registers[i].addr,
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*(uint16_t *)(dmibar+dmi_registers[i].addr),
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dmi_registers[i].name);
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break;
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case 1:
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printf("dmibase+0x%04x: 0x%02x (%s)\n",
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dmi_registers[i].addr,
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*(uint8_t *)(dmibar+dmi_registers[i].addr),
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dmi_registers[i].name);
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break;
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}
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}
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} else {
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for (i = 0; i < size; i += 4) {
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if (*(uint32_t *)(dmibar + i))
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printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(dmibar+i));
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}
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}
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unmap_physical((void *)dmibar, size);
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return 0;
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