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mb/tgl: Enable SaGv for TGL-UP3 RVP 

BUG=none
BRANCH=none
TEST=Build and boot TGL-UP3 RVP with QS silicon successfully.

Change-Id: I5b84457a1455edfe500ce80ba7f7ca6ccce43666
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43276
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Shreesh Chhabbi 2020-07-07 18:25:45 -07:00 committed by Duncan Laurie
parent a815272b7b
commit c7fe0bd8d6
1 changed files with 1 additions and 1 deletions
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2
src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
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@ -13,7 +13,7 @@ chip soc/intel/tigerlake
register "pmc_gpe0_dw2" = "GPP_E" register "pmc_gpe0_dw2" = "GPP_E"
# FSP configuration # FSP configuration
register "SaGv" = "SaGv_Disabled" register "SaGv" = "SaGv_Enabled"
register "SmbusEnable" = "1" register "SmbusEnable" = "1"
register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1 register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1