diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig
index 24f4c119cf..6242147fd0 100644
--- a/src/vendorcode/google/chromeos/Kconfig
+++ b/src/vendorcode/google/chromeos/Kconfig
@@ -65,3 +65,12 @@ config FLASHMAP_OFFSET
 	  Offset of flash map in firmware image
 
 endmenu
+
+config NO_TPM_RESUME
+	bool
+	default n
+	depends on CHROMEOS
+	help
+	  On some boards the TPM stays powered up in S3. On those
+	  boards, booting Windows will break if the TPM resume command
+	  is sent during an S3 resume.
diff --git a/src/vendorcode/google/chromeos/vboot.c b/src/vendorcode/google/chromeos/vboot.c
index 5bdb7a2b7a..0f30547056 100644
--- a/src/vendorcode/google/chromeos/vboot.c
+++ b/src/vendorcode/google/chromeos/vboot.c
@@ -39,6 +39,11 @@
 #define TPM_E_NEEDS_SELFTEST     ((u32)(TPM_E_NON_FATAL + 1))
 #define TPM_E_DOING_SELFTEST     ((u32)(TPM_E_NON_FATAL + 2))
 
+#if CONFIG_NO_TPM_RESUME
+static void init_vboot(int bootmode)
+{
+}
+#else
 static const struct {
 	u8 buffer[12];
 } tpm_resume_cmd = {
@@ -229,6 +234,7 @@ static void init_vboot(int bootmode)
 	printk(BIOS_ERR, "TPM: Error code 0x%x. Hard reset!\n", result);
 	hard_reset();
 }
+#endif
 
 void init_chromeos(int bootmode)
 {